Methods of forming bottom and top source/drain regions on a vertical transistor device

1. A method of forming a vertical transistor device, the method comprising:

forming a vertically oriented channel semiconductor structure above a substrate;

performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during said epi deposition process; and

after performing said epi deposition process, forming a gate structure around a portion of said vertically oriented channel semiconductor structure positioned vertically between said bottom source/drain region and said top source/drain region.

2. The method of claim 1 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an entirety of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.

3. The method of claim 1 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an upper portion of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.

4. The method of claim 1 , wherein said vertically oriented channel semiconductor structure and said substrate comprise different semiconductor materials.

5. The method of claim 1 , wherein forming said vertically oriented channel semiconductor structure above said substrate comprises performing at least one etching process on said substrate to define said vertically oriented channel semiconductor structure, wherein said vertically oriented channel semiconductor structure is comprised of the substrate material.

6. The method of claim 1 , wherein, after performing said epi deposition process and prior to forming said gate structure, the method further comprises forming a bottom spacer around a portion of said vertically oriented channel semiconductor structure and above said bottom source/drain region, wherein said gate structure is formed above said bottom spacer structure.

7. The method of claim 6 , further comprising forming a top spacer around a portion of said vertically oriented channel semiconductor structure and above said gate structure.

8. The method of claim 1 , wherein, prior to performing said epi deposition process, the method comprises etching a trench into said substrate around said vertically oriented channel semiconductor structure, wherein said at least a portion of said bottom source/drain region is formed in said trench.

9. The method of claim 1 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form said at least a portion of said bottom source/drain region and said at least a portion of said top source/drain region to substantially a same thickness.

10. A method of forming a vertical transistor device, the method comprising:

forming a vertically oriented channel semiconductor structure above a substrate;

performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during said epi deposition process;

forming a bottom spacer around a portion of said vertically oriented channel semiconductor structure and above said bottom source/drain region;

forming a gate structure around a portion of said vertically oriented channel semiconductor structure and above said bottom spacer, wherein said portion of said vertically oriented channel semiconductor structure is positioned between said bottom source/drain region and said top source/drain region; and

forming a top spacer around a portion of said vertically oriented channel semiconductor structure and above an upper surface of said gate structure.

11. The method of claim 10 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an entirety of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.

12. The method of claim 10 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an upper portion of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.

13. The method of claim 10 , wherein, prior to performing said epi deposition process, the method comprises etching a trench into said substrate around said vertically oriented channel semiconductor structure, wherein said at least a portion of said bottom source/drain region is formed in said trench.

14. The method of claim 10 , wherein, prior to performing said epi deposition process, the method comprises:

removing a patterned etch mask from above an upper surface of said vertically oriented channel semiconductor structure;

performing an anisotropic etching process to define a first trench in said substrate around said vertically oriented channel semiconductor structure and to remove a first portion of said vertically oriented channel semiconductor structure such that said vertically oriented channel semiconductor structure has a first recessed upper surface; and

performing an isotropic etching process to define a second trench having a greater depth and a greater lateral width than said first trench and to remove a second portion of said vertically oriented channel semiconductor structure such that said vertically oriented channel semiconductor structure has a second recessed upper surface, wherein performing said epi deposition process results in at least a portion of said bottom source/drain region being formed in said second trench and said top source/drain region being formed on said second recessed upper surface of said vertically oriented channel semiconductor structure.

15. The method of claim 10 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form said at least a portion of said bottom source/drain region and said at least a portion of said top source/drain region to substantially a same thickness.

16. A method of forming a vertical transistor device, the method comprising:

forming a vertically oriented channel semiconductor structure above a substrate by performing at least one etching process through a patterned etch mask positioned above said substrate;

removing a portion of said patterned etch mask positioned above an upper surface of said vertically oriented channel semiconductor structure;

performing an anisotropic etching process to define a first trench in said substrate around said vertically oriented channel semiconductor structure and to remove a first portion of said vertically oriented channel semiconductor structure such that said vertically oriented channel semiconductor structure has a first recessed upper surface;

performing an isotropic etching process to define a second trench having a greater depth and a greater lateral width than said first trench and to remove a second portion of said vertically oriented channel semiconductor structure such that said vertically oriented channel semiconductor structure has a second recessed upper surface;

performing an epi deposition process to simultaneously form an entirety of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process, wherein at least a portion of said bottom source/drain region is formed in said second trench and said top source/drain region is formed on said second recessed upper surface of said vertically oriented channel semiconductor structure;

forming a bottom spacer around a portion of said vertically oriented channel semiconductor structure and above said bottom source/drain region;

forming a gate structure around a portion of said vertically oriented channel semiconductor structure and above said bottom spacer, wherein said portion of said vertically oriented channel semiconductor structure is positioned between said bottom source/drain region and said top source/drain region; and

forming a top spacer around a portion of said vertically oriented channel semiconductor structure and above an upper surface of said gate structure.

17. The method of claim 16 , further comprising forming an upper source/drain contact that is conductively coupled to said upper source/drain region.