Structure and method of fabricating three-dimensional (3D) metal-insulator-metal (MIM) capacitor and resistor in semi-additive plating metal wiring

1. A method of processing a substrate, comprising:

providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer;

depositing a polymer layer atop the substrate;

patterning the polymer layer to form a plurality of openings to a top surface of the first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad;

depositing a first barrier layer atop the polymer layer and within the plurality of openings formed in the polymer layer;

depositing a dielectric layer atop the first barrier layer and within the plurality of openings formed in the polymer layer;

etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer;

depositing a second barrier layer atop the substrate;

depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and

etching the second metal layer from a portion of the field region of the polymer layer.

2. The method of claim 1 , wherein the substrate is one of silicon, glass, ceramic, or dielectric.

3. The method of claim 1 , wherein the metal pad is copper.

4. The method of claim 1 , wherein the first metal layer is titanium.

5. The method of claim 1 , wherein the polymer dielectric layer is polyimide or polybenzoxazole.

6. The method of claim 1 , wherein the polymer layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.

7. The method of claim 1 , wherein the first barrier layer is titanium nitride (TiN).

8. The method of claim 1 , wherein the second metal layer is a copper or aluminum layer.

9. The method of claim 1 , wherein the dielectric layer is hafnium oxide (HfO 2 ), silicon nitride (Si 3 N 4 ), or tantalum oxide (Ta 2 O 5 ).

10. A method of processing a substrate, comprising:

providing a substrate having a patterned polymer dielectric layer comprising a plurality of openings;

depositing a first barrier layer atop the patterned polymer dielectric layer and within the plurality of openings;

depositing a dielectric layer atop the first barrier layer;

depositing a second barrier layer atop the dielectric layer; and

depositing a metal pad atop a portion of a field region of the patterned polymer dielectric layer.

11. The method of claim 10 , wherein the substrate is one of silicon, glass, ceramic, or dielectric.

12. The method of claim 10 , wherein the metal pad is copper.

13. The method of claim 10 , wherein the patterned polymer dielectric layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.

14. The method of claim 10 , wherein at least one of the first barrier layer or the second barrier layer is titanium or titanium nitride (TiN).

15. The method of claim 10 , wherein the dielectric layer is one of hafnium oxide (HfO 2 ), silicon nitride (Si 3 N 4 ), or tantalum oxide (Ta 2 O 5 ).

16. The method of claim 10 , further comprising:

etching the first barrier layer, the dielectric layer, and the second barrier layer from the portion of the field region of the patterned polymer dielectric layer prior to depositing the metal pad atop the portion of the field region.

17. A substrate, comprising:

a polymer dielectric layer;

a metal pad filling an opening in the polymer dielectric layer;

a patterned first metal layer atop the polymer dielectric layer and conductively coupled to the metal pad;

a polymer layer atop the substrate, wherein the polymer layer comprises a plurality of openings etched to a top surface of the patterned first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad;

a barrier layer atop the polymer layer and within the plurality of openings in the polymer layer;

a dielectric layer atop the barrier layer and within the plurality of openings in the polymer layer;

a second barrier layer atop the substrate; and

a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings, and wherein the barrier layer, the dielectric layer and the second metal layer are not formed atop a portion of a field region of the substrate.

18. The substrate of claim 17 , wherein the polymer dielectric layer is polyimide or polybenzoxazole.

19. The substrate of claim 17 , wherein the polymer layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.

20. The substrate of claim 17 , wherein the second metal layer is a copper or aluminum layer.

21. The substrate of claim 17 , wherein the dielectric layer is hafnium oxide (HfO 2 ), silicon nitride (Si 3 N 4 ), or tantalum oxide (Ta 2 O 5 ).