Electronic packages with three-dimensional conductive planes, and methods for fabrication

1. An electronic package, comprising:

a first substrate;

a plurality of electrically conductive contact pads disposed on the first substrate;

a second substrate comprising a plurality of through-substrate first vias and a plurality of through-substrate second vias;

an electrically insulating adhesion layer disposed between and bonding together the first substrate and the second substrate, the adhesion layer having a thickness between the first substrate and the second substrate, and comprising a plurality of openings through the thickness, and an adhesion layer edge defining a conductive plane space between the first substrate and the second substrate;

an electrically conductive plane extending through the conductive plane space and into contact with the adhesion layer edge;

a plurality of electrically conductive first interconnects extending through respective first vias and into contact with the conductive plane; and

a plurality of electrically conductive second interconnects extending through respective second vias and openings and into contact with respective contact pads, wherein the second interconnects are electrically isolated from the electrically conductive plane.

2. The electronic package of claim 1 , wherein at least one of the first substrate and the second substrate comprises a semiconductor material.

3. The electronic package of claim 1 , comprising an electrically insulating surface, wherein the contact pads and the electrically conductive plane are disposed on the electrically insulating surface.

4. The electronic package of claim 3 , wherein the electrically insulating surface is part of an electrically insulating layer disposed on the first substrate, or is part of an electrically insulating region of the first substrate.

5. The electronic package of claim 1 , comprising an electrically insulating layer conformally covering the second substrate, including inner surfaces of the second substrate defining the respective vias.

6. The electronic package of claim 1 , wherein the first interconnects have a configuration selected from the group consisting of:

the first interconnects are conformally disposed on inner surfaces defining the respective first vias;

the first interconnects fill the respective vias; and

the first interconnects are conformally disposed on the outer edge.

7. The electronic package of claim 1 , wherein the first substrate comprises a first substrate inside surface, the second substrate comprises a second substrate inside surface facing the first substrate inside surface across the conductive plane space, and the electrically conductive plane comprises a first planar section conformally disposed on the first substrate inside surface and a second planar section conformally disposed on the second substrate inside surface.

8. The electronic package of claim 1 , wherein the electrically conductive plane fills the conductive plane space.

9. The electronic package of claim 1 , wherein the second interconnects have a configuration selected from the group consisting of:

the second interconnects are conformally disposed on inner surfaces defining the respective second vias and on inner surfaces of the adhesion layer defining the respective openings; and

the second interconnects fill the respective second vias and the respective openings.

10. The electronic package of claim 1 , wherein the adhesion layer comprises a composition selected from the group consisting of photoresist, epoxy-based photoresist, polyimide, polyparaxylylene, liquid crystal polymer, benzocyclobutene, and SU8.

11. The electronic package of claim 1 , wherein the thickness of the adhesion layer is in a range from 1 to 100 μm.

12. The electronic package of claim 1 , wherein at least one of the contact pads contacts the conductive plane.

13. The electronic package of claim 12 , wherein one of the first interconnects is aligned with the at least one contact pad that contacts the conductive plane.

14. The electronic package of claim 1 , wherein the adhesion layer edge comprises a recess aligned with one of the first interconnects.

15. The electronic package of claim 1 , wherein the conductive plane extends to an outer perimeter of at least one of the first substrate and the second substrate.

16. The electronic package of claim 1 , wherein the first substrate comprises a plurality of vias, and the contact pads are disposed in the respective vias.

17. The electronic package of claim 1 , wherein the second vias have a configuration selected from the group consisting of:

the second vias are aligned with respective contact pads;

the second vias are open to but not aligned with respective contact pads.

18. The electronic package of claim 1 , comprising an electrically conductive layer disposed on or embedded in the first substrate, and a dielectric layer disposed on the electrically conductive layer, wherein the conductive plane is disposed on the dielectric layer, and wherein the electrically conductive layer, the dielectric layer, and the conductive plane form a capacitor.

19. The electronic package of claim 18 , wherein the electrically conducting layer has a configuration selected from the group consisting of:

the electrically conductive layer is in signal communication with at least one of the contact pads;

the electrically conductive layer is in signal communication with at least one of the contact pads that contacts a second interconnect.

20. A method for fabricating an electronic package, the method comprising:

forming an electrically insulating adhesion layer on a first substrate;

patterning the adhesion layer to form a plurality of openings through the adhesion layer and an adhesion layer edge, wherein the openings expose a plurality of electrically conductive contact pads disposed on the first substrate, and the adhesion layer edge defines a conductive plane space on the first substrate in which material of the adhesion layer is absent;

aligning a second substrate with the first substrate such that first vias of the second substrate are aligned with the conductive plane space and second vias of the second substrate are aligned with the respective openings;

bonding the first substrate and the second substrate together by bringing the second substrate into contact with the adhesion layer and applying a force to at least one of the first substrate and the second substrate while heating the adhesion layer, wherein the conductive plane space is between the first substrate and the second substrate and adjacent to the adhesion layer; and

performing a metallization process to form an electrically conductive plane, a plurality of first interconnects, and a plurality of second interconnects, wherein the conductive plane extends through the conductive plane space into contact with the adhesion layer edge, the first interconnects extend through respective first vias into contact with the conductive plane, and the second interconnects extend through the respective second vias and openings and into contact with respective contact pads, and wherein the second interconnects are electrically isolated from the electrically conductive plane.

21. The method of claim 20 , comprising at least partially curing the adhesion layer prior to bonding.

22. The method of claim 20 , wherein patterning the adhesion layer comprises subjecting the adhesion layer to a photolithography process.

23. The method of claim 20 , wherein forming the adhesion layer comprises performing a step selected from the group comprising spin-coating, spray-coating, dip-coating, flow-coating, and lamination.

24. The method of claim 20 , wherein at least one of the contact pads is exposed to the conductive plane space, and contacts the conductive plane after the metallization process.

25. The method of claim 24 , wherein one of the first interconnects is aligned with the at least one contact pad that contacts the conductive plane.

26. An electronic package fabricated according to the method of claim 20 .