Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
1. An integrated circuit including at least one transistor device, the integrated circuit comprising:
a substrate having a fin extending therefrom, the fin including a first region;
a second region and a third region at least one of on or in the fin, such that the first region is between the second region and the third region;
a gate electrode above the first region, the first region between two portions of the gate electrode, the gate electrode including one or more metals;
a gate dielectric between the gate electrode and the first region;
a first spacer structure and a second spacer structure adjacent opposite sidewalls of the gate electrode, the first and second spacer structures including one or more dielectrics;
a first cap structure on and above at least a portion of the second region, the first cap structure comprising a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm −3 , wherein the first cap structure does not extend under the gate dielectric; and
a second cap structure on and above at least a portion of the third region, the second cap structure comprising a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm −3 , wherein the second cap structure does not extend under the gate dielectric;
a first contact on and above the first cap structure, the first contact including one or more metals, the first contact further including germanium; and
a second contact on and above the second cap structure, the second contact including one or more metals, the second contact further including germanium.
2. The integrated circuit of claim 1 wherein the second and third regions comprise at least one of silicon and germanium.
3. The integrated circuit of claim 1 wherein the substrate is silicon and the fin is part of the substrate, and the first and second regions comprise silicon and germanium.
4. The integrated circuit of claim 1 wherein the second and third regions at least one of:
extend above a topmost portion of the fin;
include a tip region that extends under a corresponding one of the spacer structures; or
include a tip region that extends under the gate dielectric.
5. An integrated circuit including at least one transistor device, the integrated circuit comprising:
a substrate having first and second fins extending therefrom, the first fin including a first region, and the second fin including a second region;
a source region and a drain region at least one of on or in the first fin, such that the first region is between the source and drain regions, the source and drain regions including semiconductor material and p-type dopant;
a gate electrode at least above the first region;
a gate dielectric between the gate electrode and the first region;
a first gate spacer and a second gate spacer adjacent opposite sidewalls of the gate electrode, the first and second gate spacers including dielectric material;
a first cap structure on and above at least a portion of the source region, the first cap structure not present under the gate dielectric, the first cap structure comprising a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm −3 ;
a second cap structure on and above at least a portion of the drain region, the second cap structure not present under the gate dielectric, the second cap structure comprising a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm −3 ;
a first contact on and above the first cap structure, the first contact including metal-germanide; and
a second contact on and above the second cap structure, the second contact including metal-germanide.
6. The integrated circuit of claim 5 wherein the source and drain regions comprise at least one of silicon and germanium.
7. The integrated circuit of claim 5 wherein the substrate is single crystal silicon and the fins are part of the substrate, and the source and drain regions comprise silicon and germanium and are within a faceted recess.
8. The integrated circuit of claim 5 wherein the source and drain regions at least one of:
extend above a topmost portion of the first fin;
include a tip region that extends under a corresponding one of the gate spacers; or
include a tip region that extends under the gate dielectric.
9. The integrated circuit of claim 5 , further comprising:
a second source region and a second drain region at least one of on or in the second fin, such that the second region is between the second source and drain regions, the second source and drain regions including semiconductor material and n-type dopant;
a second gate electrode above the second region;
a second gate dielectric between the second gate electrode and the second region;
third and fourth gate spacers adjacent opposite sidewalls of the second gate electrode; and
a contact on at least a portion of one of the second source and drain regions, the contact including metal-silicide.
10. The integrated circuit of claim 1 , wherein a first interface between the second region and the first cap structure and a second interface between a third region and the second cap structure have a band misalignment of less than 0.2 eV.
11. The integrated circuit of claim 5 , wherein a first interface between the source region and the first cap structure and a second interface between the drain region and the second cap structure have a band misalignment of less than 0.2 eV.
12. The integrated circuit of claim 1 , wherein the gate dielectric and the gate electrode are adjacent to three sides of the first region.
13. The integrated circuit of claim 5 , wherein the gate dielectric and the gate electrode are adjacent to three sides of the first region.