IP Library Granted Patent US 9,721,791
Granted Patent B2
US 9,721,791 · App. 15/343,966 · Granted Aug 1, 2017

Method of fabricating III-nitride semiconductor dies

Inventor: Michael A. Briere (Scottsdale, AZ)
Assignee: Infineon Technologies Americas Corp.
H01L21/0254H01L21/02002H01L21/0242H01L21/02373H01L21/02378H01L21/02381H01L21/02422H01L21/02538H01L21/30604H01L21/78H01L23/562H01L29/2003H01L2924/0002
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Quick Facts
Patent No.
US 9,721,791
App. No.
15/343,966
Granted
Aug 1, 2017
Kind
B2
Abstract

According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Claims (27)

1. A method, comprising:

growing a III-Nitride body over a group IV substrate in a semiconductor wafer;

forming at least one device layer over the III-Nitride body;

etching grid array trenches in the III-Nitride body and in the group IV substrate;

forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and

forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

2. The method of claim 1 , further comprising:

forming the grid array trenches by means of a laser scribing technique.

3. The method of claim 1 , wherein the at least one device layer is a metal layer.

4. The method of claim 1 , wherein the at least one device layer is a dielectric layer.

5. The method of claim 1 , wherein the at least one device layer is a semiconductor layer.

6. The method of claim 1 , wherein the group IV substrate is selected from the group consisting of a silicon substrate, a sapphire substrate, a silicon carbide substrate, an SOI substrate, and a SIMOX substrate.

7. A method, comprising:

growing a group III-V body over a group IV substrate in a semiconductor wafer;

forming at least one device layer over the group III-V body;

etching first trenches in the group III-V body;

forming an edge trench around a perimeter of the semiconductor wafer, the edge trench terminating inside the group IV substrate; and

forming separate dies by cutting the semiconductor wafer approximately along the first trenches.

8. The method of claim 7 , further comprising etching the first trenches in the group IV substrate.

9. The method of claim 7 , wherein the at least one device layer comprises a metal layer.

10. The method of claim 7 , wherein the at least one device layer comprises a. dielectric layer.

11. The method of claim 7 , wherein the at least one device layer is a semiconductor layer.

12. The method of claim 7 , wherein the group IV substrate comprises silicon.

13. The method of claim 7 , wherein the group IV substrate comprises sapphire.

14. The method of claim 7 , wherein the group IV substrate comprises silicon carbide.

15. The method of claim 7 , wherein the group IV substrate comprises an SOI substrate.

16. The method of claim 7 , wherein the group IV substrate comprises a SIMOX substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2017
From: BRIERE, MICHAEL A.
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 042379/0421 →
MERGER AND CHANGE OF NAME Recorded May 15, 2017
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.; INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 042379/0473 →
Continuity (4)
Continuation 14945338 · Nov 18, 2015
Division 14191910 · Feb 27, 2014
Provisional Application 61773050 · Mar 5, 2013
Related Publication 20170076937A1 · Mar 16, 2017