Nanostructure field-effect transistors with enhanced mobility source/drain regions
Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.
1. A field-effect transistor comprising:
a nanostructure including a channel region;
a gate structure overlapped with the channel region; and
a first source/drain region coupled with the channel region, the first source/drain region comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.
2. The field-effect transistor of claim 1 wherein the first layer of the first source/drain region is arranged between the second layer of the first source/drain region and the channel region.
3. The field-effect transistor of claim 2 further comprising:
a contact coupled with the first layer of the first source/drain region.
4. The field-effect transistor of claim 1 wherein the first semiconductor material is silicon-germanium and the second semiconductor material is silicon.
5. The field-effect transistor of claim 1 wherein the first semiconductor material and the second semiconductor material include one or more elements from Group IV of the Periodic Table.
6. The field-effect transistor of claim 1 wherein the first semiconductor material is indium arsenide and the second semiconductor material is indium gallium arsenide.
7. The field-effect transistor of claim 1 wherein the first semiconductor material and the second semiconductor material each include an element selected from Group III of the Periodic Table and an element selected from Group V of the Periodic Table.
8. The field-effect transistor of claim 1 further comprising:
a contact coupled with the first layer of the first source/drain region.
9. The field-effect transistor of claim 1 further comprising:
a second source/drain region coupled with the channel region, the second source/drain region comprised of a first layer of the first semiconductor material and a second layer of the second semiconductor material, and the channel region arranged between the first source/drain region and the second source/drain region.
10. The field-effect transistor of claim 9 further comprising:
a first contact coupled with the first source/drain region; and
a second contact coupled with the second source/drain region.
11. The field-effect transistor of claim 9 further comprising:
a first contact coupled with the first layer of the first source/drain region; and
a second contact coupled with the first layer of the second source/drain region.
12. The field-effect transistor of claim 1 wherein the nanostructure is a nanowire, and the first semiconductor material and the second semiconductor material are doped to have the same conductivity type.
13. The field-effect transistor of claim 1 wherein the nanostructure is supported on a top surface of a substrate, and the channel region is oriented vertically relative to the top surface.
14. The field-effect transistor of claim 1 wherein the nanostructure is supported on a top surface of a substrate, and the channel region is oriented horizontally relative to the top surface.
15. A method of forming a field effect transistor, the method comprising:
forming a nanostructure that includes a channel region;
forming a first layer of a first source/drain region coupled with the channel region and comprised of a first semiconductor material having a first electronic band gap;
forming a second layer of the first source/drain region coupled with the first layer of the first source/drain region and that is comprised of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material; and
forming a gate structure that is overlapped with the channel region.
16. The method of claim 15 further comprising:
forming a contact coupled with the first layer of the first source/drain region.
17. The method of claim 15 further comprising:
forming a second source/drain region coupled with the channel region,
wherein the second source/drain region is comprised of a first layer of the first semiconductor material and a second layer of the second semiconductor material.
18. The method of claim 17 further comprising:
forming a first contact coupled with the first layer of the first source/drain region; and
forming a second contact coupled with the first layer of the second source/drain region.
19. The method of claim 15 wherein the nanostructure is supported on a top surface of a substrate, and the channel region is oriented vertically relative to the top surface.
20. The method of claim 15 wherein the nanostructure is supported on a top surface of a substrate, and the channel region is oriented horizontally relative to the top surface.