Self-aligned contact protection using reinforced gate cap and spacer portions
A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.
1. A semiconductor structure, comprising:
a semiconductor substrate;
a source;
a drain;
a gate structure between the source and the drain, the gate structure comprising a conductive gate electrode and gate cap comprising a gate cap material, the gate cap being situated between a pair of spacers comprising a spacer material, a top portion of the gate cap having at least one divot therein filled with an etch-stop material, the etch-stop material having a better etch-stop ability than the spacer material and the gate cap material, wherein the etch-stop material is present only in the at least one divot; and
at least one source contact and at least one drain contact, a respective contact covering each of the at least one divot.
2. The semiconductor structure of claim 1 , wherein the spacer material comprises a nitride, and wherein the etch-stop material comprises one of silicon carbonitride, hafnium dioxide and aluminum (III) oxide (II).
3. The semiconductor structure of claim 1 , further comprising a layer of silicide at a boundary between each of the source and the drain and the source contact and the drain contact, respectively.
4. The semiconductor structure of claim 1 , wherein each of the source contact and the drain contact is one continuous contact, a top portion of which is surrounded by a layer of a material of the gate cap.
5. The semiconductor structure of claim 1 , wherein each of the at least one source contact and the at least one drain contact comprises a lower contact portion and an upper contact portion at least partially in physical contact and each surrounded by dielectric material.
6. The semiconductor structure of claim 1 , further comprising a fin on the semiconductor substrate, the source and the drain being integral with a top portion of the fin, and the gate electrode covering a portion of the fin between the source and the drain.
7. The semiconductor structure of claim 1 , wherein the at least one divot has a width that is less than a width of a spacer of the pair of spacers.
8. The semiconductor structure of claim 1 , wherein the at least one divot has a width that is greater than a width of a spacer of the pair of spacers, the at least one divot being situated at a top portion of both a spacer and an adjacent gate cap.
9. The semiconductor structure of claim 6 , wherein the spacer material comprises a nitride, and wherein the etch-stop material comprises one of silicon carbonitride, hafnium dioxide and aluminum (III) oxide (II).
10. The semiconductor structure of claim 6 , further comprising a layer of silicide at a boundary between each of the source and the drain and the source contact and the drain contact, respectively.
11. The semiconductor structure of claim 6 , wherein each of the source contact and the drain contact is one continuous contact, a top portion of which is surrounded by a layer of the gate cap material.
12. The semiconductor structure of claim 6 , wherein each of the at least one source contact and the at least one drain contact comprises a lower contact portion and an upper contact portion, the lower contact portion and the upper contact portion being at least partially in physical contact and each surrounded by dielectric material.