Transistor-based semiconductor device with air-gap spacers and gate contact over active area

1. A method comprising:

providing a starting semiconductor structure, the starting semiconductor structure comprising a semiconductor substrate, a fin on the semiconductor substrate, an active region having a source/drain pair with a channel region therebetween, a lower contact portion above a source and a drain of the source/drain pair, and a gate electrode over the channel region;

forming an air-gap spacer pair adjacent opposite sidewalls of the gate electrode, wherein each air-gap spacer of the air-gap spacer pair comprises an air gap that is surrounded on all sides, top and bottom by a same spacer material;

forming a lower gate contact over the gate electrode after forming the air-gap spacer pair; and

forming an upper gate contact over the lower gate contact, the upper gate contact being situated above the active region.

2. The method of claim 1 , wherein the starting semiconductor structure comprises a gate structure, the gate structure comprising the gate electrode and lower spacer portions adjacent opposite sidewalls of the gate electrode.

3. The method of claim 2 , wherein forming the air-gap spacer pair comprises:

forming the air-gap spacer pair over the lower spacer portions, the air-gap spacer pair extending to a height of the gate electrode.

4. The method of claim 3 , wherein forming the lower gate contact comprises:

forming an upwardly tapered top spacer pair over the air-gap spacer pair, resulting in a tapered gate contact opening; and

forming the lower gate contact in the tapered gate contact opening.

5. The method of claim 4 , wherein forming the upper gate contact comprises:

forming a dielectric layer over the starting semiconductor structure after forming the lower gate contact;

removing portions of the dielectric layer above the active region to expose the lower gate contact, resulting in an upper gate contact opening; and

filling the upper gate contact opening with metal.

6. The method of claim 5 , wherein the lower contact portion for each source and each drain has a dielectric cap thereon, and exposing the lower gate contact comprises:

etching the dielectric layer over the structure selective to the dielectric cap.

7. The method of claim 1 , wherein forming the lower gate contact is accomplished without a mask.

8. A semiconductor structure comprising:

a semiconductor substrate;

a semiconductor fin on the semiconductor substrate;

a transistor integrated with the semiconductor fin at a top portion thereof, the transistor comprising:

an active region comprising a source, a drain, and a channel region between the source and the drain;

a gate structure over the channel region, the gate structure comprising a gate electrode, an air-gap spacer pair adjacent opposite sidewalls of the gate electrode, each air-gap spacer of the air-gap spacer pair including an air gap that is surrounded on all sides, top and bottom by a same spacer material; and

a first lower source/drain contact disposed upon the source and a second lower source/drain contact disposed upon the drain, the first lower source/drain contact and the second lower source/drain contact each having a height extending above a height of the gate electrode; and

a gate contact for the gate electrode, the gate contact including a lower gate contact portion and an upper gate contact portion, and the lower gate contact portion having a height extending above the height of the first lower source/drain contact and the second lower source/drain contact,

wherein the upper gate contact portion includes a lower surface that is arranged over a top surface of each air-gap spacer in the air-gap spacer pair.

9. The semiconductor structure of claim 8 , wherein the air gap of each air-gap spacer of the air-gap spacer pair spans less than the height of the gate electrode.

10. The semiconductor structure of claim 8 , wherein the air gap of each air-gap spacer the air-gap spacer pair spans more than the height of the gate electrode.

11. The semiconductor structure of claim 8 , wherein the first lower source/drain contact and the second lower source/drain contact are respectively adjacent to the air gap of one of the air-gap spacers of the air-gap spacer pair.

12. The semiconductor structure of claim 11 , further comprising:

a first upper source/drain contact above the first lower source/drain contact; and

a second upper source/drain contact above the second lower source/drain contact.

13. The semiconductor structure of claim 11 , further comprising:

a first dielectric cap above the first lower source/drain contact; and

a second dielectric cap above the second lower source/drain contact.