Multi-gate device and method of fabrication thereof
A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
1. A method of fabrication of a multi-gate semiconductor device, comprising:
providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers;
removing a first portion of a first layer of the second type of epitaxial layers in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer;
forming a portion of a gate structure having a gate dielectric and a gate electrode in the opening; and
forming a dielectric material abutting the portion of the gate structure.
2. The method of claim 1 , further comprising:
forming a source/drain feature adjacent abutting the dielectric material, wherein the dielectric material interposes the source/drain feature and the gate structure.
3. The method of claim 1 , wherein the providing the fin includes
epitaxially growing the first type of epitaxial layers by growing a silicon layer; and
epitaxially growing the second type of epitaxial layers by growing a silicon germanium layer.
4. The method of claim 1 , wherein the forming the dielectric material is in a source/drain region of the fin and includes oxidizing a second portion of the first layer of the second type of epitaxial layers of the fin.
5. The method of claim 1 , wherein the forming the dielectric material is in a source/drain region of the fin and includes oxidizing a second portion of the first layer of the second type of epitaxial layers and etching the oxidized second portion before forming the gate structure.
6. The method of claim 1 , wherein the forming the dielectric material is in the source/drain region of the fin and includes etching a second portion of the first layer of the second type of epitaxial layers, and thereafter oxidizing the second portion.
7. The method of claim 1 , wherein the forming the dielectric material is in a source/drain region of the fin and includes depositing a conformal spacer material layer and etching back the conformal spacer material layer.
8. A method of fabricating a semiconductor device, comprising:
forming a first silicon layer and a second silicon layer;
forming a silicon germanium (SiGe) layer interposing the first and second silicon layers;
removing a first portion of the SiGe layer to provide an opening between the first and second silicon layers in a channel region;
providing an oxidized second portion of the SiGe layer adjacent the opening;
epitaxially growing a source/drain feature on the first and second silicon layers and abutting a sidewall of the oxidized second portion of the SiGe layer; and
forming a first region of a gate structure in the opening, wherein each of the first and second silicon layers adjacent the gate structure provide a channel.
9. The method of claim 8 , wherein the forming the first region of the gate structure includes forming a gate dielectric and a gate electrode layer in the opening.
10. The method of claim 8 , further comprising:
prior to growing the source/drain feature, etching at least a portion of the oxidized second portion of SiGe layer.
11. The method of claim 10 , wherein the growing the source/drain feature includes epitaxially growing material interfacing with a top surface and a bottom surface of the first silicon layer.
12. The method of claim 8 , wherein the providing the oxidized second portion of the SiGe layer adjacent the opening is performed by:
etching a region of the SiGe layer in a source/drain region, wherein after the etching the region, the second portion of the SiGe layer remains; and
after the etching the region of the SiGe layer in the source/drain region, performing the oxidation of the second portion.
13. The method of claim 12 , wherein the second portion underlies a spacer element abutting the gate structure.
14. The method of claim 8 , wherein the epitaxially growing the source/drain feature on the first and second silicon layers includes growing semiconductor material on a top surface of the first silicon layer and a wherein a top surface of the second silicon layer interfaces the oxidized second portion during the epitaxially growing the source/drain feature.
15. The method of claim 14 , further comprising:
forming a dummy gate structure over the first and second silicon layers and the SiGe layer, and wherein the providing the oxidized second portion of the SiGe layer includes oxidizing the SiGe layer while the dummy gate structure is disposed over the SiGe layer.