Granted Patent B2

US 12,432,956 · App. 18/404,686 · Granted Sep 30, 2025

Inventor: Ling-Yen Yeh (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H10D30/0245H01L21/3081H01L21/3085H10D30/6212H10D30/6735H10D62/121H01L21/02238H01L21/02252H01L21/02255H01L21/30604H01L21/311

Abstract

Claims (50)

1. A semiconductor device, comprising:

a plurality of semiconductor wires;

a bottom fin structure protruding from a semiconductor substrate, over which the plurality of semiconductor wires are disposed;

a gate dielectric layer wrapping around each of the plurality of semiconductor wires;

a gate electrode layer disposed over the gate dielectric layer;

an isolation insulating layer from which a source/drain semiconductor fin structure protrudes;

sidewall spacers disposed on opposite side faces of the gate electrode layer; and

a dielectric layer, made of a different material than the gate dielectric layer and the sidewall spacers, disposed between the gate electrode layer and the isolation insulating layer,

wherein a cross sectional shape of a first one of the plurality of semiconductor wires disposed furthest from the semiconductor substrate has a first shape among the plurality of semiconductor wires,

a second and a third of the plurality of semiconductor wires disposed between the first semiconductor wire and the semiconductor substrate have cross-sectional vertically extending oval shapes that are point symmetric,

the first shape is different from the vertically extending oval shapes, and

the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material.

2. The semiconductor device of claim 1 , wherein the dielectric layer includes SiON.

3. The semiconductor device of claim 1 , wherein the bottom fin structure and a bottom part of the source/drain semiconductor fin structure are continuously formed.

4. The semiconductor device of claim 3 , wherein the gate dielectric layer is disposed on a top of the bottom fin structure.

5. The semiconductor device of claim 4 , wherein the top of the bottom fin structure is rounded.

6. The semiconductor device of claim 1 , wherein the source/drain semiconductor fin structure includes recessed portions under one of the sidewall spacers.

7. The semiconductor device of claim 6 , wherein the recessed portions are located at levels between adjacent ones of the plurality of semiconductor wires.

8. The semiconductor device of claim 1 , wherein the dielectric layer includes SiOC.

9. A semiconductor device, comprising:

a plurality of nanowires disposed over a substrate;

a bottom fin structure protruding from the substrate, over which the plurality of nanowires are disposed;

a gate dielectric layer wrapping around each of the plurality of nanowires;

a gate electrode layer disposed over the gate dielectric layer; and

an isolation insulating layer from which a source/drain semiconductor fin structure protrudes,

wherein a cross sectional shape of a first one of the plurality of nanowires disposed furthest from the substrate has a largest area among the plurality of nanowires,

wherein a second and a third of the plurality of nanowires disposed between the first nanowire and the substrate have cross-sectional vertically extending oval shapes that are point symmetric, and

the bottom fin structure and a bottom part of the source/drain semiconductor fin structure are continuously formed of a same semiconductor material.

10. The semiconductor device of claim 9 , further comprising:

sidewall spacers disposed on opposite side faces of the gate electrode layer; and

a dielectric layer, different from the gate dielectric layer, disposed between the gate electrode layer and the isolation insulating layer.

11. The semiconductor device of claim 10 , wherein the dielectric layer is made of a different material than the sidewall spacers.

12. The semiconductor device of claim 10 , wherein the dielectric layer includes SiON or SiOC.

13. The semiconductor device of claim 10 , wherein the gate dielectric layer is disposed on a top of the bottom fin structure.

14. The semiconductor device of claim 13 , wherein the top of the bottom fin structure is rounded.

15. A semiconductor device, comprising:

a plurality of nanowires disposed over a semiconductor substrate;

a bottom fin structure protruding from the semiconductor substrate, over which the plurality of nanowires are disposed;

a gate dielectric layer disposed around each of the plurality of nanowires;

a gate electrode layer disposed over the gate dielectric layer;

an isolation layer from which a source/drain semiconductor fin structure extends; and

a SiON or SiOC layer disposed between the gate electrode layer and the isolation layer,

wherein the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material,

wherein a cross sectional shape of a first one of the plurality of nanowires has a largest area among the plurality of nanowires, and

wherein a second and a third of the plurality of nanowires disposed between the first nanowire and the semiconductor substrate have cross-sectional vertically extending oval shapes that are point symmetric.

16. The semiconductor device of claim 15 , wherein the plurality of nanowires are stacked over the semiconductor substrate.

17. The semiconductor device of claim 15 , wherein a width of the bottom fin structure is greater than a width of each of the plurality of nanowires.

18. The semiconductor device of claim 15 , further comprising a fourth of the plurality of nanowires having a cross-sectional vertically extending oval shape that is point symmetric.

19. The semiconductor device of claim 15 , wherein a top of the bottom fin structure is rounded.

20. The semiconductor device of claim 15 , wherein the gate dielectric layer includes silicon oxide or silicon nitride.

Assignments (1)

Continuity (4)

References Cited (76)