Method of manufacturing a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.
1. A semiconductor device, comprising:
a plurality of semiconductor wires;
a gate dielectric layer wrapping around each of the plurality of semiconductor wires; and
a gate electrode layer disposed over the gate dielectric layer,
wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires, and wherein a cross sectional shape of a bottommost one of the plurality of semiconductor wires has a smallest area among the plurality of semiconductor wires.
2. The semiconductor device of claim 1 , wherein remaining ones of the plurality of semiconductor wires have an oval shape.
3. The semiconductor device of claim 1 , further comprising:
a source/drain region which is a source/drain semiconductor fin structure;
an isolation insulating layer from which the source/drain semiconductor fin structure protrudes;
sidewall spacers disposed on opposite side faces of the gate electrode layer; and
a dielectric layer, different from the gate dielectric layer, disposed between the gate electrode layer and the isolation insulating layer.
4. The semiconductor device of claim 3 , wherein the dielectric layer is made of a different material than the sidewall spacers.
5. The semiconductor device of claim 3 , further comprising:
a bottom fin structure over which the plurality of semiconductor wires are disposed,
wherein the bottom fin structure and a bottom part of the source/drain semiconductor fin structure are continuously formed.
6. The semiconductor device of claim 5 , wherein the gate dielectric layer is disposed on a top of the bottom fin structure.
7. The semiconductor device of claim 6 , wherein the top of the bottom fin structure is rounded.
8. The semiconductor device of claim 3 , wherein the source/drain semiconductor fin structure includes recessed portions under one of the sidewall spacers.
9. The semiconductor device of claim 8 , wherein the recessed portions are located at levels between adjacent ones of the plurality of semiconductor wires.
10. The semiconductor device of claim 3 , wherein the dielectric layer includes SiON or SiOC.
11. A semiconductor device, comprising:
a plurality of semiconductor wires;
a bottom fin structure protruding from a semiconductor substrate, over which the plurality of semiconductor wires are disposed;
a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
a gate electrode layer disposed over the gate dielectric layer;
a source/drain region which is a source/drain semiconductor fin structure;
a source/drain epitaxial layer wrapping the source/drain semiconductor fin structure;
an isolation insulating layer from which the source/drain semiconductor fin structure protrudes; and
sidewall spacers disposed on opposite side faces of the gate electrode layer,
wherein the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material, wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.
12. The semiconductor device of claim 11 , wherein a cross sectional shape of a bottommost one of the plurality of semiconductor wires has a smallest area among the plurality of semiconductor wires.
13. The semiconductor device of claim 11 , further comprising:
a dielectric layer, different from the gate dielectric layer, disposed between the gate electrode layer and the isolation insulating layer,
wherein the dielectric layer is made of a different material than the sidewall spacers.
14. The semiconductor device of claim 11 , wherein the gate dielectric layer is disposed on a top of the bottom fin structure.
15. The semiconductor device of claim 14 , wherein the top of the bottom fin structure is rounded.
16. The semiconductor device of claim 11 , wherein a width of the bottom fin structure is greater than a width of each of the plurality of semiconductor wires.
17. A semiconductor device, comprising:
a plurality of semiconductor wires;
a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
a gate electrode layer disposed over the gate dielectric layer;
an isolation insulating layer from which a source/drain semiconductor fin structure protrudes;
sidewall spacers disposed on opposite side faces of the gate electrode layer; and
a dielectric layer, made of a different material than the gate dielectric layer and the sidewall spacers, disposed between the gate electrode layer and the isolation insulating layer,
wherein the dielectric layer includes SiON or SiOC, and
wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.
18. The semiconductor device of claim 17 , further comprising:
a bottom fin structure protruding from a semiconductor substrate, over which the plurality of semiconductor wires are disposed,
wherein the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material.
19. The semiconductor device of claim 17 , wherein a cross sectional shape of a bottommost one of the plurality of semiconductor wires has a smallest area among the plurality of semiconductor wires.
20. The semiconductor device of claim 18 , wherein the top of the bottom fin structure is rounded.