Semiconductor package and its manufacturing method
Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.
1. A semiconductor package comprising:
a semiconductor chip;
a first insulating film embedding the semiconductor chip and having a first via;
a first wiring over the semiconductor chip, the first wiring being electrically connected to the semiconductor chip through the first via;
a bonding film under the semiconductor chip, the bonding film having a second via; and
a second wiring under the bonding film, the second wiring being electrically connected to the semiconductor chip through the second via,
wherein a material included in the first insulating film is different from a material included in the bonding film.
2. The semiconductor package according to claim 1 ,
wherein the semiconductor chip comprises a first terminal and a second terminal under and over the semiconductor chip, respectively, and
wherein the semiconductor chip is electrically connected to the second wiring and the first wiring through the first terminal and the second terminal, respectively.
3. The semiconductor package according to claim 1 , further comprising:
a third via in the first insulating film; and
a third wiring under the first insulating film, the third wiring being electrically connected to the first wiring through the third via.
4. The semiconductor package according to claim 3 ,
wherein the second wiring and the third wiring exist in the same layer.
5. The semiconductor package according to claim 3 ,
wherein the first via, the second via, and the third via are different in size from one another.
6. The semiconductor package according to claim 1 ,
wherein the bonding film further comprises a plurality of vias.
7. The semiconductor package according to claim 3 ,
wherein the first wiring and the third wiring are connected to each other in the third via.
8. The semiconductor package according to claim 1 ,
wherein the bonding film includes an insulating material.
9. The semiconductor package according to claim 1 , further comprising a substrate over the first wiring.
10. A manufacturing method of a semiconductor package, the manufacturing method comprising:
bonding a semiconductor chip to a first substrate with a bonding film interposed therebetween;
forming a first insulating film over the semiconductor chip;
forming a first via in the first insulating film;
forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via;
forming a second via in the bonding film; and
forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.
11. The manufacturing method according to claim 10 ,
wherein the semiconductor chip comprises a first terminal and a second terminal under and over the semiconductor chip, respectively, and
wherein the first wiring and the second wiring are formed so as to be electrically connected to the semiconductor chip through the second terminal and the first terminal, respectively.
12. The manufacturing method according to claim 10 , further comprising:
forming a third via in the first insulating film simultaneously with the first via,
wherein the first wiring is formed so as to fill the third via.
13. The manufacturing method according to claim 12 , further comprising:
forming a third wiring under the third via simultaneously with the second wiring so that the third wiring is electrically connected to the first wiring.
14. The manufacturing method according to claim 12 ,
wherein the first via, the second via, and the third via are different in size from one another.
15. The manufacturing method according to claim 10 ,
wherein the second via is formed so that the bonding film comprises a plurality of vias.
16. The manufacturing method according to claim 10 ,
wherein the bonding film includes an insulating material.
17. The manufacturing method according to claim 10 ,
wherein a material included in the first insulating film is different from a material included in the bonding film.
18. The manufacturing method according to claim 12 ,
wherein the first substrate comprises an opening portion and a wiring passing through the opening portion, and
wherein the first wiring is formed so as to be electrically connected to the wiring through the third via.