IC expected data and mask data on I/O data pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
1. An integrated circuit assembly comprising:
A. a first integrated circuit including:
i. input pads, expected data pads, and mask pads;
ii. first core circuitry having inputs coupled to the input pads, a first core output, and a second core output;
iii. first buffer circuitry having an input connected to the first core output, an output connected to a first expected data pad, and a control input;
iv. second buffer circuitry having an input connected to the second core output, an output connected to a first mask pad, and a control input; and
v. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first expected data pad, a mask data input coupled to the first mask pad, and a compare strobe input coupled to a compare strobe lead; and
B. a second integrated circuit separate from the first integrated circuit, the second integrated circuit including:
i. input pads, expected data pads, and mask pads;
ii. second core circuitry having inputs coupled to the input pads, a third core output, and a fourth core output;
iii. third buffer circuitry having an input connected to the third core output, an output connected to a second expected data pad, and a control input;
iv. fourth buffer circuitry having an input connected to the fourth core output, an output connected to a second mask pad, and a control input; and
v. second comparator circuitry having an input coupled to the third core output, an expected data input coupled to the second expected data pad, a mask data input coupled to the second mask pad, and a compare strobe input coupled to a compare strobe lead.
2. The integrated circuit assembly of claim 1 in which the first expected data pad, the first mask pad, the second expected data pad, and the second mask pad are output pads for core circuitry signals and input pads for expected data and mask signals.
3. The integrated circuit assembly of claim 1 in which the control inputs of the first and second buffer circuitry are connected together and the control inputs of the third and fourth buffer circuitry are connected together.