Adaptive oscillator for clock generation
An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
1. An oscillator circuit comprising:
a first delay line coupled to a regulated supply voltage that outputs a first delayed signal;
a second delay line coupled to a droopy supply voltage that outputs a second delayed signal; and
an edge detector generating an output clock based on a relationship between the first delayed signal and the second delayed signal, the output clock having a first feedback path to an input of the first delay line and a second feedback path to an input of the second delay line.
2. The oscillator circuit of claim 1 , wherein the first delay line and the second delay line include a same number and type of elements.
3. The oscillator circuit of claim 1 , wherein the output clock is a clock that oscillates at a frequency determined by a relationship between the regulated supply voltage and the droopy supply voltage.
4. The oscillator circuit of claim 1 , wherein the edge detector comprises a Muller C-element.
5. The oscillator circuit of claim 1 , further comprising:
a voltage regulator that receives the droopy supply voltage and outputs the regulated supply voltage.
6. The oscillator circuit of claim 5 , wherein the voltage regulator comprises a low-pass filter.
7. The oscillator circuit of claim 1 , wherein the first delay line and the second delay line comprise a plurality of programmable buffers.
8. The oscillator circuit of claim 1 , wherein the relationship between the first delayed signal and the second delayed signal is based on a polarity of the first delayed signal being the same as a polarity of the second delayed signal.
9. A system comprising:
a plurality of components in an integrated circuit, the integrated circuit including a clock tree;
a frequency locked loop circuit that generates a system clock that drives the clock tree; and
an oscillator circuit within the frequency locked loop circuit comprising:
a first delay line coupled to a first voltage that outputs a first delayed signal, wherein the first voltage is a regulated supply voltage;
a second delay line coupled to a second voltage that outputs a second delayed signal, wherein the second voltage is a droopy supply voltage; and
an edge detector generating an output clock based on a relationship between the first delayed signal and the second delayed signal, the output clock having a first feedback path to an input of the first delay line and a second feedback path to an input of the second delay line.
10. The system of claim 9 , wherein the first delay line and the second delay line of the oscillator circuit include one or more of a same number and a same type of element.
11. The system of claim 9 , wherein the oscillator circuit generates a plurality of output clocks that are multiphase and are in a fixed timing relationship to each other.
12. The system of claim 9 , wherein the oscillator circuit further comprises:
a ring oscillator comprising one or more stages, wherein each stage implements an oscillator circuit and generates a clock of a different phase.