High doped III-V source/drain junctions for field effect transistors
A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e 18 to about 1e 20 atoms/cm 3 and contacting the epitaxial contacts.
1. A semiconductor device, comprising:
a fin patterned in a substrate;
a gate disposed over the fin;
a pair of epitaxial contacts comprising a III-V material over the fin and on opposing sides of the gate; and
a channel region between the pair of epitaxial contacts under the gate, the channel region comprising an undoped III-V material region between two doped III-V material regions;
wherein the undoped III-V material region and the two doped III-V material regions are discrete portions of the channel region that define sharp junctions therebetween.
2. The semiconductor device of claim 1 , wherein the doped III-V materials comprise an n-type dopant.
3. The semiconductor device of claim 1 , wherein the doped III-V materials comprise a p-type dopant.
4. The semiconductor device of claim 1 , wherein the III-V material of the pair of epitaxial contacts is doped.
5. The semiconductor device of claim 4 , wherein the III-V material of the pair of epitaxial contacts is the same as the doped III-V materials under the gate.
6. The semiconductor device of claim 1 , wherein the gate further comprises spacers along sidewalls of the gate.
7. The semiconductor device of claim 6 , wherein the doped III-V materials are positioned under the gate between the spacers and the substrate.
8. The semiconductor device of claim 6 , wherein the doped III-V material in the channel region is beneath the spacers.
9. The semiconductor device of claim 1 , further comprising a buffer layer between the channel region and the substrate.
10. The semiconductor device of claim 9 , wherein the buffer layer comprises copper doped silicon.
11. The semiconductor device of claim 9 , wherein the buffer layer has a thickness in a range from about 30 to about 150 nm.
12. The semiconductor device of claim 9 , wherein the doped III-V materials and the buffer layer are lattice matched to the undoped III-V material.
13. The semiconductor device of claim 9 , wherein the buffer layer comprises carbon doped silicon.
14. The semiconductor device of claim 9 , wherein the buffer layer is AlN, InGaAs, AlGaAs, or any combination thereof.
15. The semiconductor device of claim 9 , wherein the buffer layer has a thickness in a range from about 100 to 150 nm.
16. The semiconductor device of claim 1 , wherein the epitaxial contacts are formed over recesses within the substrate.
17. The semiconductor device of claim 1 , wherein the doped III-V materials are GaAs, InGaAS, AlGaInP, or any combination thereof.
18. The semiconductor device of claim 1 , wherein the III-V material of the epitaxial contacts comprises a dopant in an amount that is the same as in the two doped III-V material regions of the channel regions.
19. The semiconductor device of claim 1 , wherein the III-V material of the epitaxial contacts comprises a dopant in an amount that is different than a dopant in the two doped III-V material regions of the channel regions.
20. The semiconductor device of claim 1 , wherein a thickness of the updoped III-V material of the channel region is in a range from about 35 to about 45 nm.