Management of memory array with magnetic random access memory (MRAM)
View Patent ↗The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.
1. A storage device including:
a storage media comprising:
one or more byte-addressable persistent memory devices;
one or more block-addressable persistent memory devices;
a hybrid reserved area including at least a portion of said one or more byte-addressable persistent memory devices; and
a hybrid user area including at least a portion of said one or more block-addressable persistent memory devices; and
a controller coupled to said one or more byte-addressable persistent memory devices and said one or more block-addressable persistent memory devices through a high speed interface,
wherein said controller uses said hybrid reserved area to store private data.
2. The storage device of claim 1 , wherein each of said one or more byte-addressable persistent memory devices includes one or more magnetic random access memory (MRAM) arrays.
3. The storage device of claim 1 , wherein each of said one or more block-addressable persistent memory devices includes one or more NAND flash memory arrays.
4. The storage device of claim 1 , wherein said private data include boot code or metadata or both.
5. The storage device of claim 1 , wherein said controller comprises a compression and decompression circuit for compressing and decompressing data.
6. The storage device of claim 1 , wherein said controller comprises a data deduplication circuit for removing duplicate data.
7. The storage device of claim 1 , wherein said controller comprises a security circuit for encrypting and decrypting data.
8. The storage device of claim 1 , wherein said hybrid reserved area further includes another portion of said one or more block-addressable persistent memory devices.
9. The mass storage device of claim 8 , wherein said controller further uses said hybrid reserved area to store tables.
10. The mass storage device of claim 9 , wherein said controller is operable to maintain at least a portion of said tables in said another portion of said one or more block-addressable persistent memory devices.
11. The mass storage device of claim 9 , wherein periodically at least a portion of said tables are moved from said at least a portion of said one or more byte-addressable persistent memory devices to said another portion of said one or more block-addressable persistent memory devices.
12. The storage device of claim 1 , wherein hybrid user area further includes another portion of said one or more byte-addressable persistent memory devices.
13. The storage device of claim 1 , wherein said high speed interface operates in a half-duplex mode.
14. The storage device of claim 13 , wherein said high speed interface is a version of DDR interface.
15. The storage device of claim 1 , wherein said high speed interface operates in a full-duplex mode.
16. The storage device of claim 15 , wherein said high speed interface is a Universal Flash Storage (UFS) interface.
17. The storage device of claim 15 , wherein said high speed interface is a Non-Volatile Memory Express (NVME) interface.
18. The storage device of claim 1 , wherein said controller is connected to a host through a host interface.
19. The storage device of claim 18 , wherein said host interface operates in a full-duplex mode.
20. The storage device of claim 19 , wherein said host interface is a Universal Flash Storage (UFS) interface.
21. The storage device of claim 19 , wherein said host interface is a Non-Volatile Memory Express (NVME) interface.
22. The storage device of claim 18 , wherein said host interface operates in a half-duplex mode.
23. The storage device of claim 22 , wherein said host interface is a version of DDR interface.
24. The storage device of claim 18 , wherein said controller is responsive to data from said host and is operable to cache said data in said at least a portion of said one or more byte-addressable persistent memory devices.
25. The storage device of claim 24 , wherein said controller is operable to move said cached data from said at least a portion of said one or more byte-addressable persistent memory devices to said user area.