Single wire system clock signal generation
This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.
1. An integrated circuit of a single wire system, comprising:
a single wire interface from which the single wire system is configured to draw power; and
a clock circuit externally coupled to the single wire interface and configured to dynamically adapt a frequency of a clock signal based on available power of the single wire system by
detecting a voltage from the single wire interface and
generating the clock signal having the frequency based on the detected voltage.
2. The integrated circuit of claim 1 , wherein the clock circuit is configured to decrease the frequency of the clock signal based on a determination of the detected voltage being below a threshold voltage.
3. The integrated circuit of claim 1 , wherein the clock circuit is configured to adjust the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.
4. The integrated circuit of claim 1 , wherein the clock circuit is configured to:
detect a rectified voltage from the single wire interface over a period of time, and
adjust the frequency of the clock signal based on the detected rectified voltage.
5. The integrated circuit of claim 1 , wherein the clock circuit comprises at least one of:
a digital circuit comprising a plurality of frequency dividers, or
an analog circuit.
6. The integrated circuit of claim 1 , wherein the clock circuit is configured to:
cease generating the clock signal if the voltage from the single wire interface drops to zero for a period of time.
7. The integrated circuit of claim 1 , wherein the frequency is proportional to the detected voltage.
8. The integrated circuit of claim 1 , wherein the frequency is between first and second other frequencies.
9. A method comprising:
drawing power from a single wire interface of a single wire system; and
dynamically adapting a frequency of a clock signal of a clock circuit of the single wire system based on available power of the single wire system by detecting a voltage from the single wire interface and generating the clock signal having the frequency based on the detected voltage.
10. The method of claim 9 , further comprising:
decreasing the frequency of the clock signal based on a determination of the detected voltage being below a threshold voltage.
11. The method of claim 9 , further comprising:
adjusting the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.
12. The method of claim 9 , further comprising:
detecting a rectified voltage from the single wire interface over a period of time, and
adjusting the frequency of the clock signal based on the detected rectified voltage.
13. The method of claim 9 , wherein the frequency is proportional to the detected voltage.
14. The method of claim 9 , wherein the frequency is between first and second other frequencies.
15. A system comprising:
a user system; and
a single wire system coupled with the user system by a single wire, the single wire system comprising:
a single wire interface coupled to the single wire and from which the single wire system is configured to draw power;
a clock circuit externally coupled to the single wire interface and configured to dynamically adapt a frequency of a clock signal based on available power of the single wire system by
detecting a voltage from the single wire interface and
generating the clock signal having the frequency based on the detected voltage.
16. The system of claim 15 , wherein the clock circuit is configured to:
decrease the frequency of the clock signal based on a determination of the detected voltage being below a threshold voltage.
17. The system of claim 15 , wherein the clock circuit is configured to:
adjust the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.
18. The system of claim 15 , wherein the clock circuit is configured to:
detect a rectified voltage from the single wire interface over a period of time, and
adjust the frequency of the clock signal based on the detected rectified voltage.
19. The system of claim 15 , wherein the frequency is proportional to the detected voltage.
20. The system of claim 15 , wherein the frequency is between first and second other frequencies.