IP Library Granted Patent US 10,134,716
Granted Patent B2
US 10,134,716 · App. 15/460,982 · Granted Nov 20, 2018

Multi-package integrated circuit assembly with through-mold via

Inventor: Hyoung Il Kim (Folsom, CA)
Assignee: Intel Corporatin
H01L25/105H01L25/50H01L2225/1041H01L2225/1058
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Quick Facts
Patent No.
US 10,134,716
App. No.
15/460,982
Granted
Nov 20, 2018
Kind
B2
Abstract

A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.

Claims (25)

1. A multi-package integrated circuit assembly comprising:

a first electronic package including a first package substrate having a first die side and a first interface side opposing the first die side, a first die electrically coupled to the first die side of the first package substrate, the first package substrate including first contact pads exposed on the first die side, second contact pads exposed on the first interface side, and electrical routing layers therein electrically connecting the first contact pads to respective second contact pads;

a second electronic package including a second package substrate having a second die side and a second interface side opposing the second die side, a second die electrically coupled to the second die side of the second package substrate, the second interface side facing the first interface side, the second package substrate including second contact pads exposed on the second die side, third contact pads exposed on the second interface side, and electrical routing layers therein electrically connecting the third contact pads to respective fourth contact pads;

a first insulative covering located between the first interface side and the second interface side, the insulative covering disposed on and in contact with the first interface side;

a metallic plated hole extended through the first insulative covering and electrically coupling the first package substrate and the second package substrate, wherein the metallic plated hole is located from the interface side of the first package substrate to the interface side of the second package substrate;

a conductive interconnect between and in contact with the third contact pads and the metallic plated hole; and

a collective substrate attached to the first electronic, wherein the collective substrate is located on a face of the first electronic package opposing the first package substrate, and the collective substrate is electrically coupled to the first die and the second die through the first package substrate, wherein the first insulative covering is disposed on and in contact with a side of the collective substrate outside a periphery of the of first package substrate and facing the first die side.

2. The integrated circuit assembly of claim 1 , wherein at least one of the first die and the second die is a stacked die package having a plurality of dies attached together.

3. The integrated circuit assembly of claim 1 , wherein the plurality of dies of the second electronic package are electrically coupled to the collective substrate through the first package substrate.

4. The integrated circuit assembly of claim 1 , further comprising a second insulative covering located between the first die and the collective substrate and the first die and the first insulative covering.

5. The integrated circuit assembly of claim 1 , wherein the metallic plated hole is located within a periphery of the first die.

6. The integrated circuit assembly of claim 1 , further comprising a plurality of metallic plated holes located from the interface side of the first substrate to the interface side of the second substrate, wherein the plurality of metallic plated holes are located within a periphery of the first die.

7. The integrated circuit assembly of claim 1 , wherein the metallic plated hole is located between the first die and the second die.

8. The integrated circuit assembly of claim 1 , wherein the metallic plated hole is located within a periphery of the second die.

9. The integrated circuit assembly of claim 1 , wherein the metallic plated hole includes a dimension along a longitudinal axis of the metallic plated hole that is 10 μm, 500 μm, or any dimension therebetween.

10. A three-dimensional multi-package integrated circuit assembly comprising:

a first electronic package including a first package substrate having a first die side and a first interface side, a plurality of first package dies electrically coupled to the first die side of the first package substrate;

a second electronic package including a second package substrate having a second die side and a second interface side, a plurality of second package dies electrically coupled to the second die side of the second package substrate;

a first insulative covering located between the first interface side and the second interface side, the insulative covering disposed on and in contact with the first interface side;

a metallic plated hole extended through the first insulative covering and electrically coupling the first package substrate and the second package substrate, wherein the metallic plated hole is located from the interface side of the first package substrate to the interface side of the second package substrate;

a conductive interconnect between and in contact with the third contact pads and the metallic plated hole; and

a collective substrate attached to the first electronic package, wherein the collective substrate is located on a face of the first electronic package opposing the first package substrate, and the collective substrate is electrically coupled to the first package substrate and the second package substrate, and the second package substrate is electrically coupled to the collective substrate through the first package substrate, wherein the first insulative covering is disposed on and in contact with a side of the collective substrate facing the first die side.

11. The integrated circuit assembly of claim 10 , wherein the plurality of second package dies are electrically coupled to the collective substrate through the first package substrate.

12. The integrated circuit assembly of claim 10 , wherein the metallic plated hole includes a dimension along a longitudinal axis of the metallic plated hole that is 10 μm, 500 μm, or any dimension therebetween.

13. The integrated circuit assembly of claim 10 , wherein the collective substrate is electrically coupled to the plurality of first package dies and the plurality of second package dies through the first package substrate.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 043102 FRAME: 0809. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 14, 2017
From: KIM, HYOUNG IL
To: INTEL CORPORATION
Reel/Frame 043542/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KIM, HYOUNG IL
To: INTEL COPRORATION
Reel/Frame 043102/0809 →
Continuity (1)
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