Replacement low-k spacer
A semiconductor structure including a semiconductor material portion located on a substrate and extending along a lengthwise direction, a gate stack overlying a portion of the semiconductor material portion, and a first low-k spacer portion and a second low-k spacer portion abutting the gate stack and spaced from each other by the gate stack along said lengthwise direction. The first low-k spacer portion and the second low-k spacer portion each part of a recessed dummy gate structure on the substrate and a sacrificial spacer with gaps around and above a portion of the dummy gate stack. The gaps are filled in with the first low-k spacer portion and the second low-k spacer portion.
1. A semiconductor structure comprising:
a semiconductor material portion located on a substrate and extending along a lengthwise direction;
a gate stack overlying a portion of the semiconductor material portion;
a first low-k spacer portion and a second low-k spacer portion abutting the gate stack and spaced from each other by the gate stack along said lengthwise direction, wherein the first low-k spacer portion and the second low-k spacer portion are each formed around a recessed dummy gate structure and extend vertically along a sidewall of the recessed dummy gate structure prior to removal of the recessed dummy gate structure, each low-k spacer portion comprising a bottom section having a corresponding width that is constant and a top section having a corresponding width that tapers, the first low-k spacer portion coupled to a first oxide layer and the second low-k spacer portion coupled with a second oxide layer, the first low-k spacer portion and the second low-k spacer portion coupled to a replacement metal gate (RMG) structure that is disposed between the first low-k spacer portion and the second low-k spacer portion and composed of a high-k material having a dielectric constant greater than silicon oxide; and
a low-k cap layer over the RMG structure, the first low-k spacer portion and the second low-k spacer portion.
2. The semiconductor structure of claim 1 , further comprising:
a source junction coupled to the first oxide layer and the first low-k spacer portion; and
a drain junction coupled to the second oxide layer and the second low-k spacer portion; wherein the RMG structure having a top portion and a bottom portion, and the RMG structure has a width that is wider at the top portion than at the bottom portion.
3. The semiconductor structure of claim 1 , wherein:
each bottom section of each low-k spacer portion has a constant width from a top of the bottom section to a bottom of the bottom section, and each top section of each low-k spacer portion has a width that tapers from a bottom of the top section to a top of the top section;
each bottom section of each low-k spacer portion is thicker in width than any part of a top section of the low-k spacer portion, and the bottom section of the low-k spacer portion is vertically flush against a sidewall of the recessed dummy gate structure, such that the entirety of the top section is narrower than the bottom section, resulting in a gap between the sidewall of the recessed dummy gate structure and the top section of the low-k spacer portion; and
a cavity formed between the first low-k spacer portion and the second low-k spacer portion after removal of the recessed dummy gate structure is wider at a top section of the cavity than a bottom section of the cavity, the bottom section of the cavity having a constant width that is thicker than any part of the top section of the cavity.
4. The semiconductor structure of claim 1 , wherein chemical-mechanical planarization (CMP) is used to reduce a height of the low-k cap layer to an oxide layer.
5. The semiconductor structure of claim 1 , chemical-mechanical planarization (CMP) is used to reduce a height of the low-k cap layer to an oxide layer, and the low-k cap layer completely covers the gate stack.
6. The semiconductor structure of claim 1 , wherein a height of the low-k cap layer is reduced to an oxide layer.