Address fault detection in a flash memory system
View Patent ↗A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an activated word line or bit line is the word line or bit line that was actually intended to be activated based upon the received address, which will identify a type of fault where the wrong word line or bit line is activated. The address fault detection array also is used to indicate whether more than one word line or bit line was activated, which will identify a type of fault where two or more word lines or bit lines are activated.
1. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.
2. The system of claim 1 , wherein each flash memory cell in the memory array is a split gate flash memory cell.
3. The system of claim 1 , wherein each memory cell in the address fault detection array is a split gate flash memory cell.
4. The system of claim 1 , wherein each memory cell in the address fault detection array is a ROM cell.
5. The system of claim 1 , wherein each flash memory cell in the memory array is programmed through a source side hot electron programming mechanism.
6. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell programmed through a source side hot electron programming mechanism.
7. The system of claim 1 , wherein each flash memory cell in the memory array comprises a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.
8. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell comprising a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.
9. The system of claim 1 , wherein for each flash memory cell in the memory array, an erased state in a flash memory cell represents a “1” value and a programmed state in a flash memory cell represents a “0” value.
10. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell and an erased state in the flash memory cells represents a “1” value and a programmed state in the flash memory cells represents a “0” value.
11. The system of claim 1 , wherein the memory array and the address fault detection array are coupled to shared word lines and are coupled to different control gate lines, erase gate lines, and source lines.
12. The system of claim 1 , further comprising a sensing circuit for reading data in the address fault detection array.
13. The system of claim 12 , wherein the sensing circuit is a differential sensing circuit.
14. The system of claim 12 , wherein the sensing circuit is a single ended sensing circuit.
15. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein for each “0” bit in a row address, the address fault detection array stores a value of “01,” and for each “1” bit in a row address, the address fault detection array stores a value of “10”.
16. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein for each “0” bit in a row address, the address fault detection array stores a value of “10,” and for each “1” bit in a row address, the address fault detection array stores a value of “01”.
17. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein the address fault detection array comprises one or more source line transistors that pull one or more columns in the address fault detection array to ground during a power-down operation.
18. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, the columns comprising an indicator column, wherein each of the plurality of word lines is coupled to a row in the address fault detection array and each memory cell in an indicator column stores the same value;
a first comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different; and
a second comparator for comparing a current drawn by the indicator column with a reference current and for indicating a fault if the current drawn by the indicator column exceeds the reference current.
19. The system of claim 18 , wherein for each “0” bit in a row address, the address fault detection array stores a value of “01,” and for each “1” bit in a row address, the address fault detection array stores a value of “10”.
20. The system of claim 18 , wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.
21. The system of claim 18 , wherein the address fault detection array comprises a column of cells, each cell storing a “1” value.
22. The system of claim 18 , wherein each flash memory cell in the memory array is a split gate flash memory cell.
23. The system of claim 18 , wherein each memory cell in the address fault detection array is a ROM cell.
24. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a column decoder for receiving a column address as an input, the column decoder coupled to a plurality of bit lines, wherein each bit line is coupled to a column of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of bit lines is coupled to a row in the address fault detection array; and
a comparator for comparing a column address received by the column decoder with a value output from the address fault detection array in response to an assertion of a bit line by the column decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple bit lines by the column decoder;
wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.
25. The system of claim 24 , wherein the address fault detection array comprises a column of cells, each cell storing a ‘1’ value.
26. The system of claim 24 , wherein each flash memory cell in the memory array is a split gate flash memory cell.
27. The system of claim 24 , wherein each memory cell in the address fault detection array is a ROM cell.
28. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a column decoder for receiving a column address as an input, the column decoder coupled to a plurality of bit lines, wherein each bit line is coupled to a column of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of bit lines is coupled to a row in the address fault detection array; and
a comparator for comparing a column address received by the column decoder with a value output from the address fault detection array in response to an assertion of a bit line by the column decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple bit lines by the column decoder;
wherein for each “0” bit in a column address, the address fault detection array stores a value of “01,” and for each “1” bit in a column address, the address fault detection array stores a value of “10”.
29. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
a column decoder for receiving a column address as an input, the column decoder coupled to a plurality of bit lines, wherein each bit line is coupled to a column of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines and each of the plurality of bit lines is coupled to a row in the address fault detection array;
a first comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to the assertion of a word line by the row decoder and for indicating a fault if the compared values are different; and
a second comparator for comparing a column address received by the column decoder with a value output from the address fault detection array in response to the assertion of a bit line by the column decoder and for indicating a fault if the compared values are different.
30. The system of claim 29 , wherein for each “0” bit in a row or column address, the address fault detection array stores a value of “01,” and for each “1” bit in a row or column address, the address fault detection array stores a value of “10”.
31. The system of claim 29 , wherein for each “0” bit in a row or column address, the address fault detection array stores a value of “10,” and for each “1” bit in a row or column address, the address fault detection array stores a value of “01”.
32. The system of claim 29 , wherein the address fault detection array comprises one or more source line transistors that pull one or more columns in the address fault detection array to ground during a power-down operation.
33. The system of claim 29 , wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.
34. The system of claim 29 , wherein each flash memory cell in the memory array is a split gate flash memory cell.
35. The system of claim 29 , wherein each memory cell in the address fault detection array is a split gate flash memory cell.
36. The system of claim 29 , wherein each memory cell in the address fault detection array is a ROM cell.
37. The system of claim 29 , wherein each flash memory cell in the memory array is programmed through a source side hot electron programming mechanism.
38. The system of claim 29 , wherein each memory cell in the address fault detection array is a flash memory cell programmed through a source side hot electron programming mechanism.
39. The system of claim 29 , wherein each flash memory cell in the memory array comprises a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.
40. The system of claim 29 , wherein each memory cell in the address fault detection array is a flash memory cell comprising a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.
41. The system of claim 29 , wherein for each flash memory cell in the memory array, an erased state in a flash memory cell represents a “1” value and a programmed state in a flash memory cell represents a “0” value.
42. The system of claim 29 , wherein each memory cell in the address fault detection array is a flash memory cell and an erased state in the flash memory cells represents a “1” value and a programmed state in the flash memory cells represents a “0” value.
43. The system of claim 29 , wherein the memory array and the address fault detection array are coupled to different control gate lines, erase gate lines, and source lines.
44. The system of claim 29 , further comprising an analog comparator that indicates a fault if no rows have been selected.
45. The system of claim 29 , further comprising an analog comparator that indicates no fault if one and only one row has been selected.
46. The system of claim 29 , further comprising an analog comparator that indicates a fault if two or more rows have been selected.
47. The system of claim 29 , further comprising a sensing circuit for reading data in the address fault detection array.
48. The system of claim 47 , wherein the sensing circuit a differential sensing circuit.
49. The system of claim 47 , wherein the sensing circuit is a single ended sensing circuit.
50. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
a column decoder for receiving a column address as an input, the column decoder coupled to a plurality of bit lines, wherein each bit line is coupled to a column of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, the columns comprising an indicator column, wherein each of the plurality of word lines and each of the plurality of bit lines is coupled to a row in the address fault detection array and each memory cell in the indicator column stores the same value;
a first comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to the assertion of a word line by the row decoder and for indicating a fault if the compared values are different;
a second comparator for comparing a column address received by the column decoder with a value output from the address fault detection array in response to the assertion of a bit line by the column decoder and for indicating a fault if the compared values are different; and
a third comparator for comparing a current drawn by the indicator column with a reference current and for indicating a fault if the current drawn by the indicator column exceeds the reference current.
51. The system of claim 50 , wherein for each “0” bit in a row or column address, the address fault detection array stores a value of “01,” and for each “1” bit in a row or column address, the address fault detection array stores a value of “10”.
52. The system of claim 50 , wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.
53. The system of claim 50 , wherein the address fault detection array comprises a column of cells, each cell storing a ‘1’ value.
54. The system of claim 50 , wherein each flash memory cell in the memory array is a split gate flash memory cell.
55. The system of claim 50 , wherein each memory cell in the address fault detection array is a ROM cell.