IP Library Granted Patent US 10,553,456
Granted Patent B2
US 10,553,456 · App. 15/472,387 · Granted Feb 4, 2020

Semiconductor package and manufacturing method of semiconductor package

Inventors: Yasuyuki Takehara (Ishikawa, JP); Kazuhiko Kitano (Ishikawa, JP)
Assignee: J-Devices Corporation
H01L21/561H01L21/4871H01L21/76873H01L21/76874H01L23/13H01L23/142H01L23/293H01L23/295H01L23/3121H01L23/3142H01L23/544H01L24/32H01L23/4926H01L24/29H01L2223/54426H01L2223/54453H01L2224/13113H01L2224/13118H01L2224/13139H01L2224/13155H01L2224/29011H01L2224/2919H01L2224/32245
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,553,456
App. No.
15/472,387
Granted
Feb 4, 2020
Kind
B2
Abstract

A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

Claims (30)

1. A semiconductor package, comprising:

a substrate having at least one recessed portion;

a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion;

a resin insulating layer covering the semiconductor device; and

an adhesive layer between the substrate and the semiconductor device,

wherein

the adhesive layer has an opening exposing the at least one recessed portion,

an edge of the opening surrounds the at least one recessed portion in a planar view, and

any structure that comprises a conductive material and that is connected to the semiconductor device is not located at the opening.

2. The semiconductor package according to claim 1 , wherein:

the resin insulating layer is in contact with a side wall of the opening.

3. The semiconductor package according to claim 1 , wherein:

the at least one recessed portion includes at least two recessed portions; and

the at least two recessed portions are located at positions corresponding to opposing corners of the semiconductor device as seen in a planar view.

4. The semiconductor package according to claim 2 , wherein the resin insulating layer is in contact with a side wall of the at least one recessed portion.

5. The semiconductor package according to claim 4 , wherein the resin insulating layer fills the at least one recessed portion.

6. The semiconductor package according to claim 5 , wherein:

the at least one recessed portion includes at least two recessed portions; and

the at least two recessed portions are located at positions corresponding to opposing corners of the semiconductor device as seen in a planar view.

7. The semiconductor package according to claim 6 , wherein the at least two recessed portions each have a size of 0.05 mm or greater and 1.0 mm or less.

8. The semiconductor package according to claim 6 , wherein the at least two recessed portions each have a size of 0.1 mm or greater and 0.3 mm or less.

9. The semiconductor package according to claim 8 , wherein a distance between each of the at least two recessed portions and the semiconductor device is 0.05 mm or greater and 0.5 mm or less.

10. The semiconductor package according to claim 1 , wherein the edge of the opening surrounds the at least one recess portion continuously.

11. The semiconductor package according to claim 1 , wherein the edge of the opening surrounds the at least one recess portion continuously 360 degrees.

12. The semiconductor package according to claim 1 , further comprising a line connecting to the semiconductor device,

wherein

the resin insulating layer is located above the semiconductor device, and

the line is located above the semiconductor device and the resin insulating layer.

13. The semiconductor package according to claim 12 , further comprising a solder ball connecting to the line,

wherein the solder ball is located above the line.

Assignments (2)
CHANGE OF NAME Recorded Jul 17, 2020
From: J-DEVICES CORPORATION
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 053242/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2017
From: TAKEHARA, YASUYUKI; KITANO, KAZUHIKO
To: J-DEVICES CORPORATION
Reel/Frame 041777/0856 →
Priority Claims (1)
JP 2016-090189 · Apr 28, 2016 · national
Continuity (1)
Related Publication 20170316996A1 · Nov 2, 2017
Cited By (1)
US 12,266,581