IP Library Granted Patent US 10,170,392
Granted Patent B2
US 10,170,392 · App. 15/479,810 · Granted Jan 1, 2019

Wafer level integration for embedded cooling

Inventors: Timothy Joseph Chainer (Putnam Valley, NY); Pritish Ranjan Parida (Fishkill, NY); Mark Delorman Schultz (Ossining, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L23/427H01L21/82H01L25/0655H01L25/50
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Quick Facts
Patent No.
US 10,170,392
App. No.
15/479,810
Granted
Jan 1, 2019
Kind
B2
Abstract

Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

Claims (15)

1. A device, comprising:

a silicon wafer, comprising:

channel structures formed on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas; and

integrated circuits formed on a second surface of the silicon first wafer that opposes the first surface; and

a manifold wafer bonded to the first surface of the silicon wafer, wherein portions of the manifold wafer enclose the radial channels and wherein inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas.

2. The device of claim 1 , further comprising:

a thermally conductive bonding layer formed between the silicon wafer and the manifold wafer.

3. The device of claim 1 , wherein the silicon wafer comprises a plurality of integrated circuits formed on the silicon wafer.

4. The device of claim 1 , wherein the silicon wafer comprises a plurality of integrated circuits formed within the silicon wafer.

5. The device of claim 1 , further comprising an inlet path that receives liquid coolant, wherein the inlet opening distributes the liquid coolant to the radial channels,

outlet openings that expel vapor generated from the liquid coolant within the radial channels into outlet paths.

6. The device of claim 5 , further comprising outlet openings that expel vapor generated from the liquid coolant within the radial channels into outlet paths.

7. The device of claim 2 , wherein the thermally conductive bonding layer is comprised of copper.

8. The device of claim 2 , wherein the thermally conductive bonding layer is comprised of an adhesive.

9. The device of claim 8 , wherein the adhesive comprises a phenoxy thermoplastic adhesive.

Assignments (2)
CONFIRMATORY LICENSE Recorded Apr 19, 2018
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GOVERNMENT OF THE UNITED STATES AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
Reel/Frame 045984/0700 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2017
From: CHAINER, TIMOTHY JOSEPH; PARIDA, PRITISH RANJAN; SCHULTZ, MARK DELORMAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041861/0229 →
Continuity (1)
Related Publication 20180294205A1 · Oct 11, 2018
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