Granted Patent B2

US 12,199,011 · App. 18/399,127 · Granted Jan 14, 2025

Inventors: Belgacem Haba (Saratoga, CA); Gaius Gillman Fountain, Jr. (Youngsville, NC)

Assignee: Adeia Semiconductor Bonding Technologies Inc.

H01L23/433H01L24/08H01L25/0652H01L25/0657H01L24/16H01L24/32H01L24/73H01L24/80H01L2224/08225H01L2224/16225H01L2224/32225H01L2224/73204H01L2224/80895H01L2224/80896H01L2225/06517H01L2225/06541H01L2225/06582H01L2225/06589H01L2924/16151H01L2924/16196H01L2924/16235H01L2924/16251

Abstract

Claims (38)

1. A device package comprising:

an integrated cooling assembly comprising a semiconductor device and a cold plate bonded to the semiconductor device, the cold plate comprising a patterned first side and an opposite second side, wherein:

the patterned first side comprises a base surface, sidewalls, and a plurality of support features;

the base surface is spaced apart from the semiconductor device to collectively define a coolant channel therebetween;

the sidewalls slope away from the base surface at an angle greater than 90 degrees and are bonded to the semiconductor device to define a perimeter of the coolant channel;

the plurality of support features is bonded to the semiconductor device inward of the perimeter; and

each of the plurality of support features is wider at the base surface than at a bonding interface with the semiconductor device.

2. The device package of claim 1 , wherein the cold plate is bonded to the semiconductor device by direct dielectric bonds.

3. The device package of claim 1 , wherein the cold plate is bonded to the semiconductor device by direct hybrid bonds.

4. The device package of claim 1 , wherein openings in the integrated cooling assembly extend between the patterned first side and the opposite second side of the cold plate.

5. The device package of claim 1 , wherein openings in the integrated cooling assembly comprise gaps between the patterned first side of the cold plate and the semiconductor device.

6. The device package of claim 1 , further comprising:

a package substrate having the integrated cooling assembly disposed thereon;

a package cover disposed on the package substrate and extending over the integrated cooling assembly, the package cover having an inlet opening and an outlet opening disposed therethrough; and

a material layer disposed between the package cover and the cold plate, wherein

the coolant channel is in fluid communication with the inlet opening and the outlet opening through respective openings disposed through the material layer.

7. The device package of claim 6 , further comprising a coolant fluid disposed in the coolant channel.

8. The device package of claim 6 , wherein the openings in the integrated cooling assembly comprise portions of a fluid path that further comprises the inlet and outlet openings, the openings disposed through the material layer, and the coolant channel.

9. The device package of claim 6 , wherein the package cover comprises one or more coolant line attachment features.

10. The device package of claim 6 , further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in regions outside of the coolant channel.

11. The device package of claim 6 , wherein the material layer forms an impermeable barrier between the package cover and the cold plate.

12. The device package of claim 6 , wherein side surfaces of the cold plate and the semiconductor device are substantially flush with one another.

13. The device package of claim 6 , wherein:

the semiconductor device is a first semiconductor device and the integrated cooling assembly further comprises a plurality of second semiconductor devices vertically arranged in a device stack; and

the device stack is attached to the patterned first side of the cold plate in a side-by-side arrangement with the first semiconductor device.

14. The device package of claim 13 , wherein the cold plate is attached to a second semiconductor device of the plurality of second semiconductor devices by direct dielectric bonds.

15. The device package of claim 13 , wherein the cold plate is attached to a second semiconductor device of the plurality of second semiconductor devices by direct hybrid bonds.

16. The device package of claim 6 , wherein the semiconductor device is a first semiconductor device and the device package further comprises:

a device stack electrically connected to the package substrate in a side-by-side arrangement with the integrated cooling assembly; and

a first TIM layer disposed between the device stack and the package cover.

17. The device package of claim 16 , wherein the package cover comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the coolant channel.

18. The device package of claim 16 , further comprising a heat sink thermally coupled to an outside surface of the package cover, wherein the package cover comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the heat sink.

19. The device package of claim 6 , wherein:

the semiconductor device comprises a first device and a second device directly bonded to the first device;

the integrated cooling assembly comprises one or more cold plates attached to the first device; and

each of the one or more cold plates is sealed to the package cover by an adhesive layer to define perimeters of the coolant channels respectively disposed therebetween.

20. The device package of claim 19 , wherein the second device is thermally coupled to the package cover by a TIM layer disposed therebetween.

21. The device package of claim 1 , wherein the cold plate comprises sloped sidewalls are formed by a wet etch.

Assignments (1)

Continuity (2)

References Cited (146)