Packaged semiconductor device including liquid-cooled lid and methods of forming the same
Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
1. A semiconductor package comprising:
a first integrated circuit die;
a second integrated circuit die adjacent the first integrated circuit die;
an encapsulant extending between the first integrated circuit die and the second integrated circuit die;
a lid coupled to the first integrated circuit die, the second integrated circuit die, and the encapsulant, wherein the lid is coupled to the first integrated circuit die and the second integrated circuit die by dielectric-to-dielectric bonds, wherein the lid has a plurality of channels in a surface of the lid opposite the first integrated circuit die; and
a cooling cover coupled to the lid opposite the first integrated circuit die, wherein a lower surface of the cooling cover is flat, wherein the cooling cover is coupled to the lid opposite the first integrated circuit die by a plurality of screw-type fasteners, wherein the screw-type fasteners extend through the cooling cover, and wherein the lid is free from the screw-type fasteners.
2. The semiconductor package of claim 1 , wherein the lid is coupled to the encapsulant by dielectric-to-dielectric bonds.
3. The semiconductor package of claim 1 , further comprising:
a heat transfer unit coupled to the cooling cover and configured to supply a liquid coolant to the plurality of channels through the cooling cover.
4. The semiconductor package of claim 1 , further comprising a gasket between the cooling cover and the lid.
5. A semiconductor package comprising:
a substrate;
a first integrated circuit die coupled to the substrate;
a second integrated circuit die coupled to the substrate adjacent the first integrated circuit die;
a lid coupled to the first integrated circuit die and the second integrated circuit die by dielectric-to-dielectric bonds;
a cooling cover coupled to the lid, wherein the cooling cover is coupled to the lid by a screw-type fastener extending through the substrate and the cooling cover; and
a ring structure extending from the cooling cover to the substrate.
6. The semiconductor package of claim 5 , further comprising an encapsulant laterally encapsulating the first integrated circuit die and the second integrated circuit die, wherein the lid is coupled to the encapsulant by dielectric-to-dielectric bonds.
7. The semiconductor package of claim 6 , wherein a side surface of the encapsulant is coterminous with a side surface of the lid.
8. The semiconductor package of claim 5 , further comprising an interposer between the substrate and each of the first integrated circuit die and the second integrated circuit die.
9. The semiconductor package of claim 5 , wherein the cooling cover is configured to supply a liquid coolant to a channel formed in a surface of the lid opposite the first integrated circuit die.
10. The semiconductor package of claim 9 , wherein a lower surface of the cooling cover is planar.
11. The semiconductor package of claim 5 , wherein the lid comprises a plurality of recesses on an upper surface, wherein the cooling cover has a first side facing the lid, wherein the first side is flat and covers the plurality of recesses in the lid.
12. A semiconductor package comprising:
an integrated circuit die bonded to a substrate;
an encapsulant on the substrate and laterally surrounding the integrated circuit die;
a lid bonded to the integrated circuit die and the encapsulant by dielectric-to-dielectric bonds, wherein the lid has a first surface facing the integrated circuit die and a second surface facing away from the integrated circuit die, wherein the lid comprises a plurality of channels in the second surface; and
a cooling cover having a substantially planar surface bonded to the second surface of the lid, wherein the planar surface of the cooling cover extends completely over the plurality of channels, wherein the cooling cover is coupled to the lid by a screw-type fastener, wherein the screw-type fastener extends through the substrate.
13. The semiconductor package of claim 12 , further comprising a second integrated circuit die bonded to the substrate adjacent the integrated circuit die, wherein the encapsulant laterally surrounds the second integrated circuit die.
14. The semiconductor package of claim 12 , wherein the cooling cover is bonded to the lid by an adhesive.
15. The semiconductor package of claim 12 , wherein the lid comprises silicon.
16. The semiconductor package of claim 12 , wherein side surfaces of the encapsulant are aligned with side surfaces of the lid.
17. The semiconductor package of claim 12 , wherein the plurality of channels are in a cross-hatch pattern.
18. The semiconductor package of claim 12 , wherein the lid is free from the screw-type fasteners.
19. The semiconductor package of claim 12 , wherein the screw-type fasteners extend through the lid.
20. The semiconductor package of claim 19 , wherein the screw-type fasteners extend through the cooling cover.