Fin cut for taper device
A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first and second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.
1. A method of making a semiconductor device, the method comprising:
patterning a fin in a substrate;
performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end;
forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin;
disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and
performing a second etching process to remove a portion of the second cut fin.
2. The method of claim 1 , wherein the first etching process includes an anisotropic etching process.
3. The method of claim 1 , wherein the first etching process includes a reactive ion etching (RIE) process.
4. The method of claim 1 , wherein the oxide layer comprises silicon dioxide.
5. The method of claim 1 , wherein forming the oxide layer comprises performing a thermal oxidation process.
6. The method of claim 1 , wherein the second etching process includes an isotropic etching process.
7. The method of claim 1 , wherein the liner comprises silicon nitride.
8. The method of claim 1 , wherein the oxide liner along the endwall of the second fin end forms a monolayer liner having a thickness in a range from about 3 to about 10 nanometers (nm).
9. A method of making a semiconductor device, the method comprising:
patterning a fin in a substrate;
removing a portion of the fin to define a first exposed end and a second exposed end;
oxidizing a portion of the first exposed end and the second exposed end to form an oxide layer;
disposing a liner over a portion of the oxide layer; and
performing a second etching process to remove a portion of the fin.
10. The method of claim 9 , wherein removing a portion of the fin comprises performing a directional etching process.
11. The method of claim 9 , wherein removing a portion of the fin comprises an RIE process.
12. The method of claim 9 , wherein oxidizing a portion of the first exposed end and the second exposed end forms an asymmetric liner.
13. The method of claim 12 , wherein a thickness of the asymmetric liner is different along a first endwall of the fin and a second endwall of the fin.
14. The method of claim 9 , wherein a thickness of the oxide layer on the first exposed end is different from a thickness of the oxide layer on the second exposed end.
15. The method of claim 9 , wherein the liner and the oxide layer form a liner bilayer along a sidewall of the first exposed fin end.
16. The method of claim 15 , wherein the bilayer liner comprises an oxide layer.
17. The method of claim 16 , wherein the bilayer liner further comprises a nitride layer.
18. The method of claim 16 , wherein a thickness of the oxide layer is in a range from about 3 to about 10 nm.
19. The method of claim 17 , wherein a thickness of the nitride layer is in a range from about 3 to about 10 nm.
20. The method of claim 15 , wherein the substrate comprises silicon, silicon germanium, or a combination thereof.