Non-volatile memory with reduced program speed variation

1. A non-volatile storage apparatus, comprising:

a memory structure comprising a word line layer and a plurality of non-volatile memory cells; and

a control circuit connected to the memory structure, the control circuit is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.

2. The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to program the different memory cells to different final targets for the common data state to result in memory cells at a first range of one or more distances from the one or more edges of the word line layer being in a first threshold voltage distribution and memory cells at a second range of one or more distances from the one or more edges of the word line layer being in a second threshold voltage distribution that is offset from the first threshold voltage distribution.

3. The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to program the different memory cells by applying a set of program voltage pulses and performing verification using the different final targets between program voltage pulses; and

the control circuit is configured to complete programming of the different memory cells on a same number of program voltage pulse.

4. The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to program faster programming memory cells and slower programming memory cells to the common data state such that the faster programming memory cells are programmed to a first threshold voltage distribution and the slower programming memory cells are programmed to a second threshold voltage distribution that is lower in voltage than the first threshold voltage distribution; and

the slower programming memory cells are positioned further from the one or more edges of a word line layer than the faster programming memory cells.

5. The non-volatile storage apparatus of claim 1 , wherein:

the plurality of non-volatile memory cells comprise a first group of memory cells at a first range of one or more distances from the one or more edges of the word line layer and a second group of memory cells at a second range of one or more distances from the one or more edges of the word line layer, the second range of distances are greater than the first range of distances;

the control circuit is configured to program the first group of memory cells using a first set of target levels for a set of data states;

the control circuit is configured to program the second group of memory cells using a second set of target level for the set of data states;

the first set of target levels are each higher in voltage than corresponding target levels in the second set of target levels such that on completion of programming the first group of memory cells are in a first set of threshold voltage distributions and the second group of memory cells are in a second set of threshold voltage distributions that are each lower in voltage than corresponding threshold voltage distributions in the first set of threshold voltage distributions.

6. The non-volatile storage apparatus of claim 1 , wherein:

the memory structure is a monolithic three dimensional memory structure that further comprises a plurality of dielectric layers, a plurality of memory columns and plurality of isolation areas;

the word line layers are arranged alternatingly with the plurality of dielectric layers forming a stack;

the memory columns extend vertically through at least a portion of the stack, the non-volatile memory cells include portions of the memory columns;

edges of the word line layers are adjacent to the isolation areas;

memory cells closer to the isolation areas are faster programming memory cells; and

memory cells further from the isolation areas are slower programming memory cells.

7. The non-volatile storage apparatus of claim 6 , wherein:

the memory cells each include a dielectric layer;

the memory cells closer to the isolation areas have thinner dielectric layers; and

the memory cells further from the isolation areas have thicker dielectric layers.

8. The non-volatile storage apparatus of claim 6 , wherein:

the memory structure includes multiple rows of memory columns between pairs of isolation areas;

the memory columns are grouped into multiple rows of memory columns per group; and

the control circuit is configured to program different memory cells to different final targets for the common data state by using different sets of final targets for the common data state for different groups.

9. The non-volatile storage apparatus of claim 8 , wherein:

the groups comprise a first group of memory cells at a first range of one or more distances from the one or more edges of the word line layer and a second group of memory cells at a second range of one or more distances from the one or more edges of the word line layer, the second range of distances are greater than the first range of distances;

the control circuit is configured to program the first group of memory cells using a first set of target levels for a set of data states;

the control circuit is configured to program the second group of memory cells, at separate time from the first group, using a second set of target levels for the set of data states;

the first set of target levels are each higher in voltage than corresponding target levels in the second set of target levels such that on completion of programming the first group of memory cells are in a first set of threshold voltage distributions and the second group of memory cells are in a second set of threshold voltage distributions that are each lower in voltage than corresponding threshold voltage distributions in the first set of threshold voltage distributions.