CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
1. An integrated circuit structure, comprising:
a first semiconductor device over a substrate, wherein the first semiconductor device comprises:
a group IV semiconductor nanowire channel region;
a first source region and a first drain region electrically coupled with the group IV semiconductor nanowire channel region; and
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group IV semiconductor nanowire channel region; and
a second semiconductor device over the substrate, wherein the second semiconductor device comprises:
a group III-V semiconductor nanowire channel region, wherein the group III-V semiconductor nanowire channel region is co-planar with the group IV semiconductor nanowire channel region;
a second source region and a second drain region electrically coupled with the group III-V semiconductor nanowire channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group III-V semiconductor nanowire channel region.
2. The integrated circuit structure of claim 1 , wherein the first source region and first drain region are p-type, and wherein the second source region and second drain region are n-type.
3. The integrated circuit structure of claim 1 , wherein the group IV semiconductor nanowire channel region consists of germanium (Ge).
4. The integrated circuit structure of claim 1 , wherein the Group IV semiconductor nanowire channel region is within a vertical stack of Group IV semiconductor nanowire channel regions.
5. The integrated circuit structure of claim 4 , further comprising:
a pair of dielectric spacers on opposing sidewalls of the first gate stack;
extrinsic regions underneath the pair of dielectric spacers, the extrinsic regions coupled to the Group IV semiconductor nanowire channel regions and to the first source and drain regions; and
a Group III-V semiconductor material under the pair of dielectric spacers and vertically between the extrinsic regions, the Group III-V semiconductor material a same material as the group III-V semiconductor nanowire channel region.
6. The integrated circuit structure of claim 1 , wherein the Group III-V semiconductor nanowire channel region is within a vertical stack of Group III-V semiconductor nanowire channel regions.
7. The integrated circuit structure of claim 6 , further comprising:
a pair of dielectric spacers on opposing sidewalls of the second gate stack;
extrinsic regions underneath the pair of dielectric spacers, the extrinsic regions coupled to the Group III-V semiconductor nanowire channel regions and to the second source and drain regions; and
a Group IV semiconductor material under the pair of dielectric spacers and vertically between the extrinsic regions, the Group IV semiconductor material a same material as the group IV semiconductor nanowire channel region.
8. The integrated circuit structure of claim 1 , wherein the Group IV semiconductor nanowire channel region is within a vertical stack of Group IV semiconductor nanowire channel regions, wherein the Group III-V semiconductor nanowire channel region is within a vertical stack of Group III-V semiconductor nanowire channel regions, and wherein the Group IV semiconductor nanowire channel regions are laterally adjacent to vertical spaces between the Group III-V semiconductor nanowire channel regions.
9. The integrated circuit structure of claim 1 , wherein the first gate stack is on a first surface of the substrate, the second gate stack is on a second surface of the substrate.
10. The integrated circuit structure of claim 1 , further comprising:
a barrier layer on top and bottom surfaces of the group III-V semiconductor nanowire channel region, the barrier layer having a band gap wider than a band gap of the group III-V semiconductor nanowire channel region.
11. The integrated circuit structure of claim 1 , further comprising:
a transition layer wrapping around the group IV semiconductor nanowire channel region.
12. A method of fabricating an integrated circuit structure, the method comprising:
forming a first semiconductor device over a substrate, wherein forming the first semiconductor device comprises:
forming a group IV semiconductor nanowire channel region;
forming a first source region and a first drain region electrically coupled with the group IV semiconductor nanowire channel region; and
forming a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group IV semiconductor nanowire channel region; and
forming a second semiconductor device over the substrate, wherein forming the second semiconductor device comprises:
forming a group III-V semiconductor nanowire channel region, wherein the group III-V semiconductor nanowire channel region is co-planar with the group IV semiconductor nanowire channel region; forming a second source region and a second drain region electrically coupled with the group III-V semiconductor nanowire channel region; and
forming a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the group III-V semiconductor nanowire channel region.
13. The method of claim 12 , wherein the first source region and first drain region are p-type, and wherein the second source region and second drain region are n-type.
14. The method of claim 12 , wherein the group IV semiconductor nanowire channel region consists of germanium (Ge).
15. The method of claim 12 , wherein the Group IV semiconductor nanowire channel region is within a vertical stack of Group IV semiconductor nanowire channel regions, the method further comprising:
forming a pair of dielectric spacers on opposing sidewalls of the first gate stack; forming extrinsic regions underneath the pair of dielectric spacers, the extrinsic regions coupled to the Group IV semiconductor nanowire channel regions and to the first source and drain regions; and
forming a Group III-V semiconductor material under the pair of dielectric spacers and vertically between the extrinsic regions, the Group III-V semiconductor material a same material as the group III-V semiconductor nanowire channel region.
16. The method of claim 12 , wherein the Group III-V semiconductor nanowire channel region is within a vertical stack of Group III-V semiconductor nanowire channel regions, the method further comprising:
forming a pair of dielectric spacers on opposing sidewalls of the second gate stack;
forming extrinsic regions underneath the pair of dielectric spacers, the extrinsic regions coupled to the Group III-V semiconductor nanowire channel regions and to the second source and drain regions; and
forming a Group IV semiconductor material under the pair of dielectric spacers and vertically between the extrinsic regions, the Group IV semiconductor material a same material as the group IV semiconductor nanowire channel region.
17. The method of claim 12 , further comprising:
forming a barrier layer on top and bottom surfaces of the group III-V semiconductor nanowire channel region, the barrier layer having a band gap wider than a band gap of the group III-V semiconductor nanowire channel region.
18. The method of claim 12 , further comprising:
forming a transition layer wrapping around the group IV semiconductor nanowire channel region.