IP Library Granted Patent US 10,074,537
Granted Patent B2
US 10,074,537 · App. 15/586,346 · Granted Sep 11, 2018

Method of forming semiconductor structure having sets of III-V compound layers

Inventors: Chi-Ming Chen (Zhubei, TW); Po-Chun Liu (Hsinchu, TW); Chung-Yi Yu (Hsinchu, TW); Chia-Shiung Tsai (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/02507H01L21/0251H01L21/0254H01L21/02458H01L29/2003H01L29/205H01L29/66462H01L29/66522H01L29/7787
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Quick Facts
Patent No.
US 10,074,537
App. No.
15/586,346
Granted
Sep 11, 2018
Kind
B2
Abstract

A method of forming a semiconductor structure includes depositing a first III-V layer over a substrate. The method includes depositing a first III-V compound layer over the first III-V layer. Depositing the first III-V compound layer includes depositing a lower III-V compound layer. Depositing the first III-V compound layer includes depositing an upper III-V compound layer over the lower III-V compound layer, wherein the first III-V layer has a doping concentration greater than that of the upper III-V compound layer. The method includes repeating depositing III-V compound layers until a number of III-V compound layers is equal to a predetermined number of III-V compound layers. The method includes forming a second III-V compound layer an upper most III-V compound layer, wherein the second III-V compound layer is undoped or doped. The method includes forming an active layer over the second III-V compound layer.

Claims (52)

1. A method of forming a semiconductor structure, the method comprising:

depositing a first III-V layer having a first-type doping over a substrate;

depositing a first III-V compound layer over the first III-V layer, wherein depositing the first III-V compound layer comprises:

depositing a lower III-V compound layer, wherein the lower III-V compound layer is undoped or has a second doping type, and

depositing an upper III-V compound layer over the lower III-V compound layer, wherein the upper III-V compound layer has the first type doping, and the first III-V layer has a doping concentration greater than that of the upper III-V compound layer;

comparing a number of III-V compound layers to a predetermined number of III-V compound layers;

repeating depositing III-V compound layers until the number of III-V compound layers is equal to the predetermined number of III-V compound layers;

forming a second III-V compound layer over an upper most III-V compound layer, wherein the second III-V compound layer is undoped or has the second type doping; and

forming an active layer over the second III-V compound layer.

2. The method of claim 1 , wherein depositing the first III-V layer comprises depositing the first III-V layer having a p-type dopant.

3. The method of claim 1 , wherein the predetermined number of III-V layers ranges from 1 to 200.

4. The method of claim 1 , wherein depositing a lower III-V compound layer closest to the first III-V compound layer comprises forming a depletion region in the first III-V compound layer.

5. The method of claim 1 , further comprising forming a dielectric layer over the active layer.

6. The method of claim 1 , further comprising etching the active layer to expose a portion of the second III-V compound layer.

7. The method of claim 6 , further comprising forming an electrode on an exposed portion of the second III-V compound layer.

8. A method of forming a semiconductor structure, the method comprising:

depositing a first III-V layer having a first-type doping over a substrate;

repeatedly depositing a pair of layers over the first III-V layer until a predetermined number of pairs is deposited, wherein each pair of layers includes a lower III-V compound layer and an upper III-V compound layer, the lower III-V compound layer is undoped or has a second doping type, and the first III-V layer has a doping concentration greater than that of the upper III-V compound layer;

forming a second III-V compound layer over an upper most III-V compound layer, wherein the second III-V compound layer is undoped or has the second type doping; and

forming an active layer over the second III-V compound layer.

9. The method of claim 8 , further comprising forming a gate electrode over the active layer.

10. The method of claim 9 , further comprising forming source/drain electrodes in contact with the second III-V compound layer, wherein forming the source/drain electrodes comprises forming the source/drain electrodes simultaneously with forming the gate electrode.

11. The method of claim 10 , wherein forming the source/drain electrodes comprises:

etching the active layer to expose a portion of the second III-V compound layer; and

depositing a metal layer over the active layer and the exposed portion of the second III-V compound layer.

12. The method of claim 9 , further comprising depositing a dielectric layer over the active layer, wherein the dielectric layer is between the gate electrode and the active layer.

13. The method of claim 8 , wherein depositing the first III-V layer comprises depositing the first III-V layer directly on the substrate.

14. The method of claim 8 , wherein the predetermined number of pairs of layers ranges from 1 to 200.

15. The method of claim 8 , wherein repeatedly depositing the pair of layers comprises depositing each pair of layers to have a same total thickness.

16. A method of forming a semiconductor structure, the method comprising:

depositing a first III-V layer having a first-type doping over a substrate;

depositing a III-V compound layer over the first III-V layer, wherein depositing the first III-V compound layer comprises:

depositing a lower III-V compound layer, wherein the lower III-V compound layer includes a dopant having the second doping type, and

depositing an upper III-V compound layer over the lower III-V compound layer, wherein the upper III-V compound layer has the first type doping, and the first III-V layer has a doping concentration greater than that of the upper III-V compound layer;

repeating depositing the III-V compound layer until a number of III-V compound layers is equal to the predetermined number of III-V compound layers;

forming a second III-V compound layer over an upper most III-V compound layer, wherein the second III-V compound layer is undoped or has the second type doping; and

forming an active layer over the second III-V compound layer.

17. The method of claim 16 , wherein depositing the second III-V compound layer comprises depositing the second III-V compound layer having a thickness less than a thickness of the upper most III-V compound layer.

18. The method of claim 16 , wherein depositing the III-V compound layer comprises:

depositing a first lower III-V compound layer over the first III-V layer;

depositing a first upper III-V compound layer over the first lower III-V compound layer, wherein a total thickness of the first lower III-V compound layer and the first upper III-V compound layer is a first thickness;

depositing a second lower III-V compound layer over the first upper III-V compound layer; and

depositing a second upper III-V compound layer over the second lower III-V compound layer, wherein a total thickness of the second lower III-V compound layer and the second upper III-V compound layer is a second thickness different from the first thickness.

19. The method of claim 16 , wherein depositing the III-V compound layer comprises:

depositing a first lower III-V compound layer over the first III-V layer, wherein the first lower III-V compound layer is undoped;

depositing a first upper III-V compound layer over the first lower III-V compound layer;

depositing a second lower III-V compound layer over the first upper III-V compound layer, wherein the second lower III-V compound layer includes the second dopant type; and

depositing a second upper III-V compound layer over the second lower III-V compound layer.

20. The method of claim 16 , further comprising:

etching the active layer to expose a portion of the second III-V compound layer;

depositing a metal layer over the active layer and the exposed portion of the second III-V compound layer; and

etching the metal layer to define a gate electrode and source/drain electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2017
From: CHEN, CHI-MING; LIU, PO-CHUN; YU, CHUNG-YI; TSAI, CHIA-SHIUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 042235/0346 →
Continuity (3)
Division 14824131 · Aug 12, 2015
Continuation 13743045 · Jan 16, 2013
Related Publication 20170236709A1 · Aug 17, 2017