IP Library Granted Patent US 10,347,729
Granted Patent B2
US 10,347,729 · App. 15/590,459 · Granted Jul 9, 2019

Device for improving performance through gate cut last process

Inventors: Xusheng Wu (Ballston Lake, NY); Haigou Huang (Rexford, NY)
Assignee: GLOBALFOUNDRIES Inc.
H01L29/42356H01L21/823431H01L21/845H01L27/0886H01L29/0649H01L29/401H01L29/4991H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 10,347,729
App. No.
15/590,459
Granted
Jul 9, 2019
Kind
B2
Abstract

Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

Claims (10)

1. A device comprising:

a plurality of fins;

an STI layer;

a high k material on a top surface of the STI layer and surrounding the fins;

a metal gate stack over the high k material;

a gate contact metal directly over the metal gate stack and conforming, on a bottom surface, to a shape of the fins; and

an inter-layer dielectric in a rectangular space adjacent to the high k material, the metal gate stack, and the gate contact metal, the inter-layer dielectric having a side surface in the rectangular space with a first portion that directly contacts the metal gate stack and a second portion that directly contacts the gate contact metal, the first portion of the side surface of the inter-layer dielectric arranged directly above the second portion of the side surface of the inter-layer dielectric.

2. The device of claim 1 , wherein the metal gate stack comprises TiN.

3. The device of claim 1 , wherein the high k material comprises aluminum oxide, hafnium silicate, zirconium silicate, hafnium oxide, or zirconium oxide.

4. The device of claim 1 , wherein a third portion of the side surface of the inter-layer dielectric directly contacts the high k material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2017
From: WU, XUSHENG; HUANG, HAIGOU
To: GLOBALFOUNDRIES INC.
Reel/Frame 042302/0176 →
Continuity (2)
Division 15187080 · Jun 20, 2016
Related Publication 20170365676A1 · Dec 21, 2017