Method for manufacturing 3D NAND memory using gate replacement, and resulting structures
A 3D memory device includes a plurality of vertical pillars composed of a vertical channel and a multilayer data storage structure. The multilayer data storage structure can comprise a dielectric charge trapping structure. A stack of dielectric lined conductive strips separated in the stack by insulating strips have sidewalls disposed adjacent the corresponding vertical pillars. The conductive strips have a dielectric liner having a dielectric constant κ greater than 7 on the sidewalls in contact with the outside layer of the multilayer data storage structure on the corresponding pillar. The conductive strips in embodiments described herein can comprise a relatively low resistance material, such as a metal or a metal nitride. A manufacturing method using Si—Ge selective etching of sacrificial layers can be used in a gate replacement process to form the dielectric conductive strips.
1. A manufacturing method, comprising: forming a vertical pillar having a sidewall, and comprising a vertical channel and multilayer data storage structure having an outside surface on the sidewall; and forming a stack of conductive strips separated in the stack by insulating strips, the conductive strips having upper and lower surfaces and sidewalls including dielectric liners having a dielectric constant K greater than 7 lining the upper and lower surfaces of the conductive strips and the sidewalls, the dielectric liners of the conductive strips in the stack in contact with the outside surface of the multilayer data storage structure of the vertical pillar.
2. The method of claim 1 , wherein said forming a vertical pillar comprises:
forming alternating layers of an insulating material and a sacrificial material;
etching trenches in the alternating layers to form a plurality of stacks of sacrificial strips separated by the insulating strips in the stacks;
forming multilayer data storage structures on the sidewalls of the trenches;
forming a semiconductor channel material over the multilayer data storage structures in the trenches; and
etching holes through the semiconductor channel material to form a plurality of vertical pillars including the first mentioned vertical pillar in the trenches, the holes exposing the sacrificial strips between the vertical pillars in the plurality of vertical pillars.
3. The method of claim 2 , wherein said forming a stack of conductive strips separated in the stacks by insulating strips comprises:
selectively removing the sacrificial strips in the stacks to form voids between the insulating strips;
lining the voids with a dielectric material to form the dielectric liners; and
filling the voids over the dielectric liners with a word line material to form the conductive strips.
4. The method of claim 3 , wherein the sacrificial material comprises germanium and the vertical channel comprises silicon.
5. The method of claim 3 , wherein the sacrificial material comprises silicon and the vertical channel comprises germanium or silicon-germanium.
6. The method of claim 3 , wherein the sacrificial material comprises germanium or silicon-germanium.
7. The method of claim 3 , wherein the conductive word line material comprises a metal.
8. The method of claim 1 , wherein the dielectric liners comprise a material different than the insulating strips.
9. The method of claim 1 , wherein the multilayer data storage structure comprises a tunneling layer, a dielectric charge storage layer and a blocking layer, and where an outside layer of the multilayer data storage structure is the blocking layer.
10. A memory device including a plurality of memory cells, comprising:
a vertical pillar having a sidewall, and comprising a vertical channel and multilayer data storage structure having an outside surface on the sidewall; and
a stack of conductive strips separated in the stack by insulating strips, the conductive strips having upper and lower surfaces and sidewalls and including dielectric liners having a dielectric constant κ greater than 7 lining the upper and lower surfaces of the conductive strips and the sidewalls in contact with the outside surface of the multilayer data storage structure.
11. The memory device of claim 10 , wherein the conductive strips comprise a metal.
12. The memory device of claim 10 , wherein the vertical channel comprises germanium or silicon-germanium.
13. The memory device of claim 10 , wherein the dielectric liners comprise a material different than the insulating strips.
14. The memory device of claim 10 , wherein the multilayer data storage structure comprises a tunneling layer, a dielectric charge storage layer and a blocking layer, and where an outside layer of the multilayer data storage structure is the blocking layer.