High density memory with reference memory using grouped cells and corresponding operations
A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.
1. A memory, comprising:
a data memory comprising a plurality of memory cells on a plurality of bit lines;
a reference memory comprising a plurality of memory cells;
conversion circuitry to convert signals from a group of memory cells including more than one member in the plurality of memory cells in the reference memory into a reference signal; and
a sense amplifier, connected to the conversion circuitry and to a bit line in the plurality of bit lines in the data memory, to sense data stored in a selected memory cell in the data memory in response to comparison of a data signal from the selected memory cell and the reference signal,
wherein the memory includes first and second physically distinct regions, the first physically distinct region of the memory respectively comprising a first physically distinct portion of the reference memory and a first physically distinct portion of the data memory and the second physically distinct region of the memory respectively comprising a second physically distinct portion of the reference memory and a second physically distinct portion of the data memory, each of the first and the second physically distinct portions of the reference memory having one or more of the plurality of memory cells in the reference memory and each of the first and the second physically distinct portions of the data memory having one or more of the plurality of memory cells in the data memory,
wherein the conversion circuitry comprises a switch enabling, responsive to the selected memory cell being from the first physically distinct portion of the data memory of the first physically distinct region of the memory, selecting the group of memory cells from the first physically distinct portion of the reference memory of the first physically distinct region of the memory,
wherein the memory further comprises on chip control circuits to control a threshold voltage trim operation for the reference memory to a current level that is a factor higher than a target sensing current, and
wherein the threshold voltage trim operation affects at least some of the plurality of memory cells in the first physically distinct portion of the reference memory and at least some of the plurality of memory cells in the second physically distinct portion of the reference memory.
2. The memory of claim 1 , wherein the group of memory cells is disposed on a plurality of local reference bit lines and the plurality of local reference bit lines are connectable together for program operations in the reference memory.
3. The memory of claim 1 ,
wherein the reference memory comprises a stack structure including a plurality of slices, each slice including a stack of horizontal word lines in respective levels of the stack and a set of vertical conductors, the plurality of memory cells in the reference memory have horizontal channels between adjacent vertical conductors at the levels of horizontal word lines in the stack, and at least one of the plurality of slices includes the group of memory cells, and
wherein the switch is a first switch and the memory further comprises at least a second switch to disconnect at least one other one of the plurality of slices from the conversion circuitry.
4. The memory of claim 3 , wherein an edge layer of the stack is included in the first physically distinct region of the memory and an interior layer of the stack is included in the second physically distinct region of the memory.
5. The memory of claim 1 , wherein the memory includes a third physically distinct region that is physically distinct from the first and the second physically distinct regions of the memory, the third physically distinct region of memory comprising (i) a third physically distinct portion of the reference memory having one or more of the plurality of memory cells in the reference memory, and (ii) a third physically distinct portion of the data memory having one or more of the plurality of memory cells in the data memory.
6. The memory of claim 1 , further comprising a capacitor in a signal path from the reference memory to the conversion circuitry, the capacitor having a capacitance to compensate for different capacitances on paths from the reference memory and the data memory to the conversion circuitry.
7. The memory of claim 1 , wherein the conversion circuitry comprises a current-to-voltage converter and a current mirror circuit enabled to produce a reference current in response to combined current from the group of memory cells, the reference current being divided in magnitude by a ratio of relative effective transistor widths of two transistors of the current mirror circuit.
8. The memory of claim 7 , wherein the switch enables selectively connecting and disconnecting, to and from a current mirror gate reference, a reference tile.
9. The memory of claim 8 , further comprising an NMOS transistor having a gate terminal coupled to the current mirror gate reference and a drain terminal coupled to a current-to-voltage convertor to produce a voltage reference coupled to an input of the sense amplifier.
10. The memory of claim 1 , further comprising a current mirror circuit enabled to preserve process, voltage, and temperature (PVT) conditions in the reference memory.
11. The memory of claim 1 , wherein the data memory and the reference memory comprise respective matching memory structures in which a combination of signals from the plurality of memory cells in the reference memory tracks process, voltage, and temperature (PVT) characteristics of the plurality of memory cells in the data memory.
12. The memory of claim 1 , wherein the reference memory is configured to have process, voltage, and temperature (PVT) characteristics that match those of the data memory and the configuring comprises arranging the reference memory and the data memory to have a same three-dimensional arrangement.
13. The memory of claim 12 , wherein the configuring further comprises dimensioning the memory cells in the reference memory and the memory cells in the data memory to identical dimensions.
14. The memory of claim 12 ,
wherein the reference memory comprises a stack structure including a plurality of slices, each slice including a stack of horizontal word lines in respective levels of the stack and a set of vertical conductors, the plurality of memory cells in the reference memory have horizontal channels between adjacent vertical conductors at the levels of horizontal word lines in the stack, and at least one of the plurality of slices includes the group of memory cells,
wherein the configuring further comprises disposing an active one of the slices between dummy ones of the slices, and
wherein the active slice comprises the group of memory cells.
15. The memory of claim 12 , wherein the configuring further comprises including, in the first physically distinct region of the memory, the memory cells having relatively similar PVT conditions with respect to each other and including, in the second physically distinct region of the memory, the memory cells having relatively similar PVT conditions with respect to each other.
16. A memory, comprising:
a data memory comprising a plurality of memory cells on a plurality of bit lines;
a reference memory comprising a plurality of memory cells, the reference memory including inactive memory cells and an active group of memory cells, the active group of memory cells connected to local reference bit lines, and to a reference word line;
conversion circuitry to convert signals on the local reference bit lines from the active group of memory cells into a reference signal; and
a sense amplifier, connected to the conversion circuitry and to a bit line in the plurality of bit lines in the data memory, to sense data stored in a selected memory cell in the data memory in response to a data signal from the selected memory cell and the reference signal,
wherein the memory includes first and second physically distinct regions, the first physically distinct region of the memory respectively comprising a first physically distinct portion of the reference memory and a first physically distinct portion of the data memory and the second physically distinct region of the memory respectively comprising a second physically distinct portion of the reference memory and a second physically distinct portion of the data memory, each of the first and the second physically distinct portions of the reference memory having one or more of the plurality of memory cells in the reference memory and each of the first and the second physically distinct portions of the data memory having one or more of the plurality of memory cells in the data memory,
wherein the conversion circuitry comprises a switch enabling, responsive to the selected memory cell being from the first physically distinct portion of the data memory of the first physically distinct region of the memory, selecting the active group of memory cells from the first physically distinct portion of the reference memory of the first physically distinct region of the memory,
wherein the memory further comprises on chip control circuits to control a threshold voltage trim operation for the reference memory to a current level that is a factor higher than a target sensing current, and
wherein the threshold voltage trim operation affects at least some of the plurality of memory cells in the first physically distinct portion of the reference memory and at least some of the plurality of memory cells in the second physically distinct portion of the reference memory.
17. The memory of claim 16 , wherein an edge layer of a stack structure comprises the first physically distinct region of the memory and an interior layer of the stack structure comprises the second physically distinct region of the memory.
18. A method of sensing memory, comprising:
converting signals from a group of memory cells into a reference signal, wherein the group of memory cells includes more than one member of a plurality of memory cells in a reference memory of a memory; and
sensing data stored in a selected memory cell in response to comparison of a data signal from the selected memory cell and the reference signal, wherein the selected memory cell is in a data memory of the memory, the data memory comprises a plurality of memory cells on a plurality of bit lines, and the data signal is carried on one of the bit lines,
wherein the memory includes first and second physically distinct regions, the first physically distinct region of the memory respectively comprising a first physically distinct portion of the reference memory and a first physically distinct portion of the data memory and the second physically distinct region of the memory respectively comprising a second physically distinct portion of the reference memory and a second physically distinct portion of the data memory, each of the first and the second physically distinct portions of the reference memory having one or more of the plurality of memory cells in the reference memory and each of the first and the second physically distinct portions of the data memory having one or more of the plurality of memory cells in the data memory,
wherein the converting signals comprises selecting, responsive to the selected memory cell being from the first physically distinct portion of the data memory of the first physically distinct region of the memory, the group of memory cells from the first physically distinct portion of the reference memory of the first physically distinct region of the memory,
wherein the method further includes controlling a threshold voltage trim operation for the reference memory to a current level that is a factor higher than a target sensing current and reducing current by the factor using a current mirror circuit that is enabled to preserve process, voltage, and temperature (PVT) conditions in the reference memory, and
wherein the threshold voltage trim operation affects at least some of the plurality of memory cells in the first physically distinct portion of the reference memory and at least some of the plurality of memory cells in the second physically distinct portion of the reference memory.
19. The method of sensing memory of claim 18 , wherein the reference memory comprises a stack structure including a plurality of slices, each slice including a stack of horizontal word lines in respective levels of the stack and a set of vertical conductors, the plurality of memory cells in the reference memory have horizontal channels between adjacent vertical conductors at the levels of horizontal word lines in the stack, and at least one of the plurality of slices includes the group of memory cells; and wherein the method further comprises disconnecting at least one other one of the plurality of slices from circuitry that performs the converting signals.
20. The method of sensing memory of claim 18 , wherein the controlling the threshold voltage trim operation for the reference memory is performed by a wafer sort tool.