Low-cost semiconductor device manufacturing method
Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.
1. A semiconductor structure, comprising:
a first buried layer of a first conductivity type formed in a semiconductor substrate;
a second buried layer of a second conductivity type formed on the first buried layer;
a drift region of the first conductivity type formed on the second buried layer;
a body region formed adjacent to the drift region;
a well region of the second conductivity type formed adjacent to the body region;
a gate electrode formed over the drift region and the body region;
a spacer formed next to the gate electrode;
a source region formed overlapping the spacer;
a body contact region of the second conductivity type formed in the body region;
a drain region formed in the drift region; and
a channel region formed in the body region between the source region and the drift region.
2. The structure of claim 1 , wherein the source region overlaps the gate electrode.
3. The structure of claim 1 , wherein a width of the first buried layer is wider than a width of the second buried layer.
4. The structure of claim 1 , wherein the well region abuts the first buried layer.
5. The structure of claim 1 , wherein the well region abuts the second buried layer and the body region.
6. The structure of claim 1 , wherein a doping concentration of the body region is higher than a doping concentration of the well region.
7. A semiconductor structure, comprising:
a first buried layer of a first conductivity type formed in a substrate;
a first well region of the first conductivity type formed on the first buried layer;
a second well region of a second conductivity type formed on the first buried layer;
a drain region formed in the first well region;
a source region formed in the second well region;
a gate electrode formed over the first well region and the second well region;
a body contact region of the second conductivity type formed in the second well region; and
a channel region formed in the second well region between the source region and the first well region,
wherein the source region overlaps the gate electrode,
wherein the first well region abuts the second well region, and
wherein the first buried layer abuts the first well region and the second well region.
8. The structure of claim 7 , further comprising:
a body region formed adjacent to the first well region.
9. The structure of claim 7 , wherein the body contact region is spaced apart from the source region.
10. The structure of claim 7 , further comprising:
a third well region of the first conductivity type formed in the substrate, and abutting the first buried layer.
11. The structure of claim 10 , wherein the second well region is surrounded by the first well region, the first buried layer and the third well region.
12. The structure of claim 1 , further comprising:
an oxide layer formed on the drift region, comprising a first oxide layer portion and a second oxide layer portion having different thicknesses,
wherein a bottom surface of the second oxide layer portion and a top surface of the substrate are on different planes.
13. A semiconductor structure, comprising:
a first buried layer of a first conductivity type formed in a substrate;
a first well region of the first conductivity type formed on the first buried layer;
a second well region of a second conductivity type formed adjacent to the first well region;
a first gate electrode formed over the first well region;
a second gate electrode formed spaced apart from the first gate electrode; a silicide layer formed between the first gate electrode and the second gate electrode;
a first doped region of the first conductivity type formed in the first well region;
a second doped region of the second conductivity type formed in the second well region;
a cathode contact formed on the first doped region;
an anode contact formed on the silicide layer; and
a third well region of the second conductivity type formed adjacent to the first well region,
wherein the second well region and the third well region surround the first well region.
14. The structure of claim 13 , further comprising:
a first guard ring of the second conductivity type formed adjacent to one side of the silicide layer;
a second guard ring of the second conductivity type formed adjacent to another side of the silicide layer;
a first field oxide layer formed under the first gate electrode; and
a second field oxide layer formed under the second gate electrode,
wherein the first and second guard rings are formed in the first well region.
15. The structure of claim 13 , wherein a Schottky contact is formed between the silicide layer and the first well region.
16. The structure of claim 13 , further comprising an isolation ring contact formed on the third well region.