IP Library Granted Patent US 10,510,757
Granted Patent B2
US 10,510,757 · App. 15/615,873 · Granted Dec 17, 2019

Semiconductor device including storage element

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1052G11C11/405G11C16/0433H01L27/105H01L27/115H01L27/1156H01L27/11551H01L27/11803H01L27/124H01L27/1207H01L27/1225H01L27/1255H01L29/16H01L29/24H01L29/247H01L29/7869H01L29/78693H01L29/78696G11C2211/4016H01L21/8221H01L27/0688H01L27/108H01L29/7833
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,510,757
App. No.
15/615,873
Granted
Dec 17, 2019
Kind
B2
Abstract

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Claims (67)

1. A semiconductor device comprising:

a plurality of storage elements,

wherein one of the plurality of storage elements includes:

a first transistor including:

a first gate electrode;

one of a first source electrode and a first drain electrode; and

the other of the first source electrode and the first drain electrode;

a second transistor including:

a second gate electrode;

one of a second source electrode and a second drain electrode; and

the other of the second source electrode and the second drain electrode; and

a third transistor including:

a third gate electrode;

one of a third source electrode and a third drain electrode; and

the other of the third source electrode and the third drain electrode,

wherein the first transistor is provided in a substrate including a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and the one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the other of the first source electrode and the first drain electrode and the one of the third source electrode and the third drain electrode are electrically connected to each other, and

wherein the first transistor operates at a speed higher than that of the second transistor.

2. The semiconductor device according to claim 1 ,

wherein the semiconductor device comprises a first wiring, a second wiring, a third wiring, a fourth wiring and a fifth wiring,

wherein the plurality of storage elements is connected in parallel between the first wiring and the second wiring,

wherein the first wiring and the one of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the second wiring and the other of the third source electrode and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the third gate electrode are electrically connected to each other.

3. The semiconductor device according to claim 1 , wherein the first transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the one of the first source electrode and the first drain electrode and the other of the first source electrode and the first drain electrode electrically connected to the impurity regions.

4. The semiconductor device according to claim 1 , wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the one of the second source electrode and the second drain electrode and the other of the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the third transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a third gate insulating layer over the channel region, the third gate electrode over the third gate insulating layer, and the one of the third source electrode and the third drain electrode and the other of the third source electrode and the third drain electrode electrically connected to the impurity regions.

6. The semiconductor device according to claim 1 , wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

7. The semiconductor device according to claim 1 , wherein the semiconductor material is silicon.

8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises an In—Ga—Zn—O-based oxide semiconductor material.

9. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a crystal of In 2 Ga 2 ZnO 7 .

10. The semiconductor device according to claim 1 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 /cm 3 or less.

11. The semiconductor device according to claim 1 , wherein an off-state current of the second transistor is 1×10 −13 A or less.

12. A semiconductor device comprising:

a first wiring, a second wiring, and a plurality of storage elements connected in parallel between the first wiring and the second wiring,

wherein one of the plurality of storage elements includes:

a first transistor including:

a first gate electrode;

one of a first source electrode and a first drain electrode; and

the other of the first source electrode and the first drain electrode;

a second transistor including:

a second gate electrode;

one of a second source electrode and a second drain electrode; and

the other of the second source electrode and the second drain electrode; and

a third transistor including:

a third gate electrode;

one of a third source electrode and a third drain electrode; and

the other of the third source electrode and the third drain electrode,

wherein the first transistor is provided in a substrate including a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and the one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring and the one of the first source electrode and the first drain electrode are electrically connected to each other,

wherein the other of the first source electrode and the first drain electrode and the one of the third source electrode and the third drain electrode are electrically connected to each other,

wherein the second wiring and the other of the third source electrode and the third drain electrode are electrically connected to each other.

13. The semiconductor device according to claim 12 , wherein the first transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the one of the first source electrode and the first drain electrode and the other of the first source electrode and the first drain electrode electrically connected to the impurity regions.

14. The semiconductor device according to claim 12 , wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the one of the second source electrode and the second drain electrode and the other of the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

15. The semiconductor device according to claim 12 , wherein the third transistor includes a channel region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel region, a third gate insulating layer over the channel region, the third gate electrode over the third gate insulating layer, and the one of the third source electrode and the third drain electrode and the other of the third source electrode and the third drain electrode electrically connected to the impurity regions.

16. The semiconductor device according to claim 12 , wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

17. The semiconductor device according to claim 12 , wherein the semiconductor material is silicon.

18. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer comprises an In—Ga—Zn—O-based oxide semiconductor material.

19. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer includes a crystal of In 2 Ga 2 ZnO 7 .

20. The semiconductor device according to claim 12 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 /cm 3 or less.

21. The semiconductor device according to claim 12 , wherein an off-state current of the second transistor is 1×10 −13 A or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2017
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; KATO, KIYOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 043156/0491 →
Priority Claims (1)
JP 2009-251261 · Oct 30, 2009 · national
Continuity (5)
Continuation 15175190 · Jun 7, 2016
Continuation 14804478 · Jul 21, 2015
Continuation 14336107 · Jul 21, 2014
Division 12914672 · Oct 28, 2010
Related Publication 20170271338A1 · Sep 21, 2017
Cited By (8)
US 12,205,622 US 12,211,534 US 12,266,398 US 12,382,664 US 12,382,723 US 12,414,335 US 12,482,418 US 12,550,447