Semiconductor device and dynamic logic circuit
View Patent ↗A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.
1. A semiconductor device comprising:
a first layer comprising a plurality of processing engines; and
a second layer over the first layer,
wherein the second layer comprises a plurality of embedded memory devices each including a peripheral circuit and a memory cell array,
wherein the memory cell array comprises a plurality of memory cells arranged in a matrix,
wherein each of the plurality of embedded memory devices overlaps with each of the plurality of processing engines,
wherein each of the plurality of processing engines comprises a silicon transistor,
wherein the peripheral circuit comprises a transistor including an oxide semiconductor,
wherein each of the plurality of memory cells comprises a first transistor, a second transistor, and a third transistor,
wherein each of the first transistor, the second transistor, and the third transistor includes a gate, a back gate, and the oxide semiconductor, and
wherein different voltages are input to the back gate of the first transistor, the back gate of the second transistor, and the back gate of the third transistor.
2. The semiconductor device according to claim 1 ,
wherein at least one of the plurality of processing engines is electrically connected to the memory cell array through the peripheral circuit.
3. The semiconductor device according to claim 1 ,
wherein each of the plurality of memory cells further comprises a retention node and a capacitor,
wherein a first terminal of the capacitor is electrically connected to the gate of the one of the first transistor, the second transistor, and the third transistor, and
wherein a second terminal of the capacitor is electrically connected to a read bit line.
4. The semiconductor device according to claim 1 ,
wherein all the transistors in the memory cell array include the oxide semiconductor.
5. The semiconductor device according to claim 1 ,
wherein all the transistors in the peripheral circuit and the memory cell array include the oxide semiconductor.
6. A semiconductor device comprising:
a first layer comprising a plurality of processing engines; and
a second layer over the first layer,
wherein the second layer comprises a plurality of embedded memory devices each including a peripheral circuit and a memory cell array,
wherein the memory cell array comprises a plurality of memory cells arranged in a matrix,
wherein each of the plurality of embedded memory devices overlaps with each of the plurality of processing engines,
wherein each of the plurality of processing engines comprises a silicon transistor,
wherein each of the plurality of memory cells comprises a first transistor, a second transistor, and a third transistor,
wherein each of the first transistor, the second transistor, and the third transistor includes a gate, a back gate, and an oxide semiconductor, and
wherein different voltages are input to the back gate of the first transistor, the back gate of the second transistor, and the back gate of the third transistor.