Semiconductor device comprising conductive layers functioning as first and second gate electrodes of a transistor
A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
1. A semiconductor device comprising:
a first transistor;
a second transistor; and
a capacitor,
wherein the first transistor comprises a first channel formation region including silicon,
wherein the second transistor comprises a second channel formation region,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one electrode of the capacitor,
wherein a first insulating layer is provided over the first channel formation region,
wherein a first conductive layer in contact with a top surface of the first insulating layer comprises a region configured to function as the gate electrode of the first transistor,
wherein a second insulating layer is provided over the first conductive layer,
wherein a second conductive layer in contact with a top surface of the second insulating layer is configured to function as a first gate electrode of the second transistor,
wherein a third insulating layer is provided in contact with a top surface of the second conductive layer,
wherein a fourth insulating layer is provided in contact with a top surface of the third insulating layer,
wherein an oxide semiconductor layer in contact with a top surface of the fourth insulating layer comprises the second channel formation region,
wherein a fifth insulating layer is provided over the oxide semiconductor layer,
wherein a third conductive layer in contact with a top surface of the fifth insulating layer is configured to function as a second gate electrode of the second transistor,
wherein a fourth conductive layer in contact with a top surface of the oxide semiconductor layer comprises a region configured to function as the one of the source electrode and the drain electrode of the second transistor,
wherein a fifth conductive layer in contact with the top surface of the oxide semiconductor layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor,
wherein a sixth conductive layer in contact with the top surface of the fifth insulating layer overlaps with the fourth conductive layer,
wherein a seventh conductive layer provided over the sixth conductive layer is electrically connected to the fifth conductive layer,
wherein an eighth conductive layer in contact with the top surface of the second insulating layer overlaps with the fourth conductive layer,
wherein the seventh conductive layer comprises a region overlapping the second channel formation region and a region overlapping the capacitor,
wherein the second conductive layer and the eighth conductive layer comprise a same material, and
wherein the third conductive layer and the sixth conductive layer comprise a same material.
2. A semiconductor device comprising:
a first transistor; and
a second transistor,
wherein the first transistor comprises a first channel formation region including silicon,
wherein the second transistor comprises a second channel formation region,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein a first insulating layer is provided over the first channel formation region,
wherein a first conductive layer in contact with a top surface of the first insulating layer comprises a region configured to function as the gate electrode of the first transistor,
wherein a second insulating layer is provided over the first conductive layer,
wherein a second conductive layer in contact with a top surface of the second insulating layer is configured to function as a first gate electrode of the second transistor,
wherein a third insulating layer is provided over the second conductive layer,
wherein an oxide semiconductor layer in contact with a top surface of the third insulating layer comprises the second channel formation region,
wherein a fourth insulating layer is provided over the oxide semiconductor layer,
wherein a third conductive layer in contact with a top surface of the fourth insulating layer is configured to function as a second gate electrode of the second transistor,
wherein a fourth conductive layer in contact with a top surface of the oxide semiconductor layer comprises a region configured to function as the one of the source electrode and the drain electrode of the second transistor,
wherein a fifth conductive layer in contact with the top surface of the oxide semiconductor layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor,
wherein a sixth conductive layer in contact with the top surface of the fourth insulating layer overlaps with the fourth conductive layer,
wherein a seventh conductive layer in contact with the top surface of the second insulating layer overlaps with the fourth conductive layer,
wherein the second conductive layer and the seventh conductive layer comprise a same material, and
wherein the third conductive layer and the sixth conductive layer comprise a same material.
3. A semiconductor device comprising:
a first transistor;
a second transistor; and
a capacitor,
wherein the first transistor comprises a first channel formation region including silicon,
wherein the second transistor comprises a second channel formation region,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one electrode of the capacitor,
wherein a first insulating layer is provided over the first channel formation region,
wherein a first conductive layer in contact with a top surface of the first insulating layer comprises a region configured to function as the gate electrode of the first transistor,
wherein a second insulating layer is provided over the first conductive layer,
wherein a second conductive layer in contact with a top surface of the second insulating layer is configured to function as a first gate electrode of the second transistor,
wherein a third insulating layer is provided in contact with a top surface of the second conductive layer,
wherein a fourth insulating layer is provided in contact with a top surface of the third insulating layer,
wherein an oxide semiconductor layer in contact with a top surface of the fourth insulating layer comprises the second channel formation region,
wherein a fifth insulating layer is provided over the oxide semiconductor layer,
wherein a third conductive layer in contact with a top surface of the fifth insulating layer is configured to function as a second gate electrode of the second transistor,
wherein a fourth conductive layer in contact with a top surface of the oxide semiconductor layer comprises a region configured to function as the one of the source electrode and the drain electrode of the second transistor,
wherein a fifth conductive layer in contact with the top surface of the oxide semiconductor layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor,
wherein a sixth conductive layer in contact with the top surface of the fifth insulating layer overlaps with the fourth conductive layer,
wherein a seventh conductive layer provided over the sixth conductive layer is electrically connected to the fifth conductive layer,
wherein an eighth conductive layer in contact with the top surface of the second insulating layer overlaps with the fourth conductive layer,
wherein the seventh conductive layer comprises a region overlapping the second channel formation region and a region overlapping the capacitor,
wherein the second conductive layer and the eighth conductive layer comprise a same material,
wherein the third conductive layer and the sixth conductive layer comprise a same material, and
wherein a thickness of the fourth insulating layer is greater than a thickness of the third insulating layer.
4. The semiconductor device according to claim 2 , wherein a thickness of the fourth insulating layer is greater than a thickness of the third insulating layer.
5. The semiconductor device according to claim 1 , wherein the seventh conductive layer comprises a region overlapping with the first channel formation region.
6. The semiconductor device according to claim 2 , wherein the seventh conductive layer comprises a region overlapping with the first channel formation region.
7. The semiconductor device according to claim 3 , wherein the seventh conductive layer comprises a region overlapping with the first channel formation region.
8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.
9. The semiconductor device according to claim 2 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.
10. The semiconductor device according to claim 3 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.