IP Library Granted Patent US 10,872,981
Granted Patent B2
US 10,872,981 · App. 16/707,432 · Granted Dec 22, 2020

Semiconductor device comprising an oxide semiconductor

Inventors: Shunpei Yamazaki (Setagaya, JP); Daisuke Matsubayashi (Atsugi, JP); Keisuke Murayama (Chigasaki, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/7831
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Quick Facts
Patent No.
US 10,872,981
App. No.
16/707,432
Granted
Dec 22, 2020
Kind
B2
Abstract

A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Claims (68)

1. A semiconductor device comprising:

a first conductive layer over an insulating surface;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer comprising a first oxide semiconductor layer and a second oxide semiconductor layer, the oxide semiconductor layer comprises a region overlapping with the first conductive layer with the first insulating layer interposed therebetween;

a second conductive layer and a third conductive layer, each of which comprises a region over and in direct contact with the second oxide semiconductor layer;

a second insulating layer comprising a region in direct contact with the oxide semiconductor layer and positioned over the oxide semiconductor layer, the second conductive layer and the third conductive layer; and

a fourth conductive layer comprising a region overlapping with the oxide semiconductor layer with the second insulating layer interposed therebetween,

wherein the second oxide semiconductor layer is provided over the first oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a region in direct contact with the first insulating layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises at least indium and gallium,

wherein the first oxide semiconductor layer further comprises tin,

wherein the first conductive layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, and

wherein the fourth conductive layer comprises indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

2. The semiconductor device according to claim 1 , wherein a thickness of the first oxide semiconductor layer is more than or equal to 3 nm and less than or equal to 15 nm.

3. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor layer is provided in a channel region of a transistor, and

wherein the transistor is a channel-etched transistor.

4. The semiconductor device according to claim 1 ,

wherein an indium content in the first oxide semiconductor layer is higher than a gallium content,

wherein an indium content in the second oxide semiconductor layer is lower than a gallium content,

wherein the first oxide semiconductor layer comprises a crystal with a size greater than or equal to 1 nm and less than 10 nm, and

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal part.

5. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer comprising a first oxide semiconductor layer and a second oxide semiconductor layer, the oxide semiconductor layer comprises a region overlapping with the first conductive layer with the first insulating layer interposed therebetween;

a second conductive layer and a third conductive layer, each of which is electrically connected to and provided over the second oxide semiconductor layer; and

a second insulating layer comprising a region in direct contact with the oxide semiconductor layer and positioned over the oxide semiconductor layer, the second conductive layer and the third conductive layer,

wherein the second oxide semiconductor layer is provided over the first oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a region in direct contact with the first insulating layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises at least indium, gallium, and zinc,

wherein the first oxide semiconductor layer further comprises tin,

wherein a thickness of the first oxide semiconductor layer is more than or equal to 3 nm and less than or equal to 15 nm, and

wherein the first conductive layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium.

6. The semiconductor device according to claim 5 ,

wherein an indium content in the first oxide semiconductor layer is higher than a gallium content,

wherein an indium content in the second oxide semiconductor layer is lower than a gallium content,

wherein the first oxide semiconductor layer comprises a crystal with a size greater than or equal to 1 nm and less than 10 nm, and

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal part.

7. The semiconductor device according to claim 5 ,

wherein the oxide semiconductor layer is provided in a channel region of a transistor, and

wherein the transistor is a channel-etched transistor.

8. The semiconductor device according to claim 5 , further comprising:

a fourth conductive layer comprising a region overlapping with the oxide semiconductor layer with the second insulating layer interposed therebetween,

wherein the fourth conductive layer comprises indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

9. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer comprising a first oxide semiconductor layer and a second oxide semiconductor layer, the oxide semiconductor layer comprises a region overlapping with the first conductive layer with the first insulating layer interposed therebetween;

a second conductive layer and a third conductive layer, each of which is electrically connected to the second oxide semiconductor layer;

a second insulating layer comprising a region in direct contact with the oxide semiconductor layer and positioned over the oxide semiconductor layer, the second conductive layer and the third conductive layer; and

a fourth conductive layer comprising a region overlapping with the oxide semiconductor layer with the second insulating layer interposed therebetween,

wherein the second oxide semiconductor layer is provided over the first oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a region in direct contact with the first insulating layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises at least indium and gallium,

wherein the first oxide semiconductor layer further comprises tin,

wherein the second conductive layer and the third conductive layer each contain an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W, and

wherein the fourth conductive layer comprises indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

10. The semiconductor device according to claim 9 , wherein the first conductive layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium.

11. The semiconductor device according to claim 9 ,

wherein an indium content in the first oxide semiconductor layer is higher than a gallium content,

wherein an indium content in the second oxide semiconductor layer is lower than a gallium content,

wherein the first oxide semiconductor layer comprises a crystal with a size greater than or equal to 1 nm and less than 10 nm, and

wherein the second oxide semiconductor layer comprises a c-axis aligned crystal part.

12. The semiconductor device according to claim 9 ,

wherein the oxide semiconductor layer is provided in a channel region of a transistor, and

wherein the transistor is a channel-etched transistor.

13. The semiconductor device according to claim 9 , wherein a thickness of the first oxide semiconductor layer is more than or equal to 3 nm and less than or equal to 15 nm.

Priority Claims (1)
JP 2012-091539 · Apr 13, 2012 · national
Continuity (5)
Continuation 16180210 · Nov 5, 2018
Continuation 15262547 · Sep 12, 2016
Continuation 14594991 · Jan 12, 2015
Continuation 13860792 · Apr 11, 2013
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