Semiconductor device
It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
1. A semiconductor device comprising:
a first node;
a second node;
a third node;
a first transistor;
a second transistor; and
a third transistor,
wherein the third node is configured to be supplied with a fixed potential,
wherein the first transistor is configured to work as a switching element to control connection between the first node and the second node,
wherein the second transistor is configured to control supply of a data potential from a data signal line to a gate electrode of the first transistor,
wherein the third transistor is configured to work as a switching element to control connection between the second node and the third node, and
wherein the gate electrode of the first transistor is in a floating state when the second transistor is in an off-state.
2. The semiconductor device according to claim 1 , wherein the second transistor is configured to control supply of the data potential from the data signal line to a gate electrode of the third transistor.
3. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are n-type, and the third transistor is p-type.
4. The semiconductor device according to claim 1 , wherein the third node is grounded.
5. The semiconductor device according to claim 1 , wherein the semiconductor device is configured to supply the fixed potential to the second node when the first transistor is in an off-state.
6. The semiconductor device according to claim 1 , wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.
7. The semiconductor device according to claim 1 , further comprising a capacitor between the gate electrode of the first transistor and the third node.
8. The semiconductor device according to claim 1 ,
wherein the first transistor comprises a channel formation region comprising silicon,
wherein the second transistor comprises a channel formation region comprising an oxide semiconductor, and
wherein the second transistor is positioned over the first transistor with an insulating film therebetween.
9. A semiconductor device comprising:
a first node;
a second node;
a third node;
a first transistor;
a second transistor; and
a resistor,
wherein the third node is configured to be supplied with a fixed potential,
wherein the first transistor is configured to work as a switching element to control connection between the first node and the second node,
wherein the second transistor is configured to control supply of a data potential from a data signal line to a gate electrode of the first transistor,
wherein the resistor is provided between the second node and the third node, and
wherein the gate electrode of the first transistor is in a floating state when the second transistor is in an off-state.
10. The semiconductor device according to claim 9 , wherein the first transistor and the second transistor are n-type.
11. The semiconductor device according to claim 9 , wherein the third node is grounded.
12. The semiconductor device according to claim 9 , wherein the semiconductor device is configured to supply the fixed potential to the second node when the first transistor is in an off-state.
13. The semiconductor device according to claim 9 , wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.
14. The semiconductor device according to claim 9 , further comprising a capacitor between the gate electrode of the first transistor and the third node.
15. The semiconductor device according to claim 9 ,
wherein the first transistor comprises a channel formation region comprising silicon,
wherein the second transistor comprises a channel formation region comprising an oxide semiconductor, and
wherein the second transistor is positioned over the first transistor with an insulating film therebetween.
16. A semiconductor device comprising:
a first node;
a second node;
a third node;
a first transistor;
a second transistor; and
a third transistor,
wherein the first transistor is configured to work as a switching element to control connection between the first node and the second node,
wherein the second transistor is configured to control supply of a data potential from a data signal line to a gate electrode of the first transistor,
wherein the third transistor is configured to work as a switching element to control connection between the second node and the third node, and
wherein the gate electrode of the first transistor is in a floating state when the second transistor is in an off-state.
17. The semiconductor device according to claim 16 , wherein the second transistor is configured to control supply of the data potential from the data signal line to a gate electrode of the third transistor.
18. The semiconductor device according to claim 16 , wherein the first transistor and the second transistor are n-type, and the third transistor is p-type.
19. The semiconductor device according to claim 16 , wherein the semiconductor device is configured to supply a fixed potential to the second node when the first transistor is in an off-state.
20. The semiconductor device according to claim 16 ,
wherein the first transistor comprises a channel formation region comprising silicon,
wherein the second transistor comprises a channel formation region comprising an oxide semiconductor, and
wherein the second transistor is positioned over the first transistor with an insulating film therebetween.