IP Library Granted Patent US 10,113,248
Granted Patent B2
US 10,113,248 · App. 15/623,077 · Granted Oct 30, 2018

Group III nitride crystal substrate, epilayer-containing group III nitride crystal substrate, semiconductor device and method of manufacturing the same

Inventors: Keiji Ishibashi (Hyogo, JP); Yusuke Yoshizumi (Hyogo, JP); Shugo Minobe (Hyogo, JP)
Assignee: Sumitomo Electric Industries, Ltd.
C30B33/00C30B21/02C30B29/403Y10T428/21Y10T428/24355
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,113,248
App. No.
15/623,077
Granted
Oct 30, 2018
Kind
B2
Abstract

A group III nitride crystal substrate is provided, wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.7×10 −3 , and wherein a plane orientation of the main surface has an inclination angle equal to or greater than −10° and equal to or smaller than 10° in a [0001] direction with respect to a plane including a c axis of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

Claims (21)

1. A wafer comprising a semiconductor device structure including a group III nitride crystal substrate and at least one semiconductor layer provided by epitaxial growth on a main surface of said crystal substrate, wherein,

a plane spacing of arbitrary specific parallel crystal lattice planes of said crystal substrate being obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a main surface of said crystal substrate while X-ray diffraction conditions of said specific parallel crystal lattice planes of said crystal substrate are satisfied,

a uniform distortion at a surface layer of said crystal substrate represented by a value of |d 1 −d 2 |/d 2 is equal to or lower than 1.7×10 −3 where d 1 indicates a plane spacing at said X-ray penetration depth of 0.3 μm and d 2 indicates a plane spacing at said X-ray penetration depth of 5 μm, and wherein

a plane orientation of said main surface has an inclination angle equal to or greater than −10° and equal to or smaller than 10° in a [0001] direction with respect to any of {10-10}, {11-20} and {21-30} planes of crystal substrate,

wherein said semiconductor layer includes a light emitting layer emitting light having a peak wavelength equal to or more than 500 nm and equal to or less than 550 nm.

2. A wafer comprising a semiconductor device structure including a group III nitride crystal substrate and at least one semiconductor layer provided by epitaxial growth on a main surface of said crystal substrate, wherein,

on a diffraction intensity profile of arbitrary specific parallel crystal lattice planes of said crystal substrate being obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a main surface of said crystal substrate while X-ray diffraction conditions of said specific parallel crystal lattice planes are satisfied,

an irregular distortion at a surface layer of said crystal substrate represented by a value of |v 1 −v 2 | obtained from a half value width v 1 of a diffraction intensity peak at said X-ray penetration depth of 0.3 μm and a half value width v 2 of the diffraction intensity peak at said X-ray penetration depth of 5 μm is equal to or lower than 110 arcsec, and wherein

a plane orientation of said main surface has an inclination angle equal to or greater than −10° and equal to or smaller than 10° in a [0001] direction with respect to any of {10-10}, {11-20} and {21-30} planes of said crystal substrate,

wherein said semiconductor layer includes a light emitting layer emitting light having a peak wavelength equal to or more than 500 nm and equal to or less than 550 nm.

3. A wafer comprising a semiconductor device structure including a group III nitride crystal substrate and at least one semiconductor layer provided by epitaxial growth on a main surface of said crystal substrate, wherein,

on a rocking curve being measured by varying an X-ray penetration depth from a main surface of said crystal substrate in connection with X-ray diffraction of arbitrary specific parallel crystal lattice planes of said crystal substrate,

a plane orientation deviation of said specific parallel crystal lattice planes of a surface layer of said crystal substrate represented by a value of |w 1 −w 2 | obtained from a half value width w 1 of a diffraction intensity peak at said X-ray penetration depth of 0.3 μm and a half value width w 2 of the diffraction intensity peak at said X-ray penetration depth of 5 μm is equal to or lower than 300 arcsec, and wherein

a plane orientation of said main surface has an inclination angle equal to or greater than −10° and equal to or smaller than 10° in a [0001] direction with respect to any of {10-10}, {11-20} and {21-30} planes of said crystal substrate,

wherein said semiconductor layer includes a light emitting layer emitting light having a peak wavelength equal to or more than 500 nm and equal to or less than 550 nm.

4. The wafer according to claim 1 , wherein said main surface has a surface roughness Ra of 5 nm or lower.

5. The wafer according to claim 1 , wherein the plane orientation of said main surface has an inclination angle equal to or greater than 0° and smaller than 0.1° with respect to any of {10-10}, {11-20} and {21-30} planes of said crystal substrate so as to be substantially parallel thereto.

6. The wafer according to claim 1 , wherein the plane orientation of said main surface has an inclination angle equal to or greater than 0.1° and equal to or smaller than 10° with respect to any of {10-10}, {11-20} and {21-30} planes of said crystal substrate.

7. The wafer according to claim 1 , wherein oxygen present at said main surface has a concentration of equal to or more than 2 at. % and equal to or less than 16 at. %.

8. The wafer according to claim 1 , wherein a dislocation density at said main surface is equal to or less than 1×10 7 cm −2 .

9. The wafer according to claim 1 , having a diameter equal to or more than 40 mm and equal to or less than 150 mm.

Assignments (1)
NUNC PRO TUNC ASSIGNMENT Recorded Dec 7, 2023
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUBISHI CHEMICAL CORPORATION
Reel/Frame 065817/0967 →
Priority Claims (4)
JP 2005-183111 · Jun 23, 2005 · national
JP 2009-206109 · Sep 7, 2009 · national
JP 2009-287970 · Dec 18, 2009 · national
WO PCT/JP2010/051158 · Jan 28, 2010 · international
Continuity (5)
Continuation 13526061 · Jun 18, 2012
Continuation In Part 12837872 · Jul 16, 2010
Continuation In Part 12216236 · Jul 1, 2008
Division 11473122 · Jun 23, 2006
Related Publication 20170283988A1 · Oct 5, 2017