Low capacitance electrostatic discharge (ESD) devices
The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.
1. A structure comprising:
a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and
a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.
2. The structure of claim 1 , wherein the first structure is a first fin structure partly over a buried oxide layer and the first well, and the second structure is a second fin structure over the second well in a bulk substrate.
3. The structure of claim 2 , wherein the first diffusion region is a P+ diffusion region, the first well is an N-well region, the second well is a P-well region and the fourth diffusion is an N+ region, forming a PNPN SCR.
4. The structure of claim 3 , wherein the second fin structure is formed at an edge of a bulk substrate material and the first fin structure is formed of semiconductor on insulator (SOI) material.
5. The structure of claim 4 , wherein the SOI material is fully depleted SOI material.
6. The structure of claim 1 , wherein:
the first structure is a fin structure;
the first diffusion region is P+ diffusion material;
the second diffusion region is N+ diffusion material; and
the third diffusion region is P+ diffusion material.
7. The structure of claim 1 , further comprising a first diode comprising the first diffusion region and a second well.
8. The structure of claim 7 , further comprising a second diode comprising a second fin structure and the second well.
9. The structure of claim 8 , wherein the first diode and the second diode are formed over a buried oxide layer of an SOI region.
10. The structure of claim 1 , further comprising a first diode comprising a fin structure of alternating diffusion regions.
11. The structure of claim 10 , wherein the first diode is provided in an SOI region, isolated from a well structure by a buried oxide layer.
12. A structure comprising:
a first P+ region of a first structure partly over a first N− region in semiconductor on insulator (SOI) technology; and
a first P− region in a bulk substrate with a first N+ region of a second structure formed at an edge of the bulk substrate, adjacent to the SOI technology.
13. The structure of claim 12 , wherein the first P+ region is partly formed on a buried oxide layer of the SOI technology.
14. The structure of claim 12 , wherein the first P+ region is formed from fully depleted semiconductor material of the SOI technology.
15. The structure of claim 13 , wherein the first structure is a first fin structure and the second structure is a second fin structure.
16. The structure of claim 13 , further comprising a first diode comprising a second P+ region and a second N-region over the buried oxide layer in an SOI region.
17. The structure of claim 16 , wherein the first P+ region and the first N− region are segmented and at an edge of the bulk technology and the SOI region.
18. The structure of claim 17 , wherein the second P+ region and the second N− region are on an SOI region.
19. A structure, comprising:
a first fin structure comprising a pattern of alternating diffusion regions extending partly over a first well and a buried oxide layer in a semiconductor on insulator (SOI) region; and
a second fin structure composed of a diffusion region and on a second well in a bulk region of a substrate, adjacent to the SOI region.
20. The structure of claim 19 , wherein the first fin structure includes a P+ region, the first well is an N-well, the second well is a P-well and the diffusion region of the second fin structure is an N-diffusion, forming a PNPN silicon controlled rectifier (SCR).