Integrated circuits with Peltier cooling provided by back-end wiring
A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.
1. A semiconductor structure comprising:
a P substrate;
an N band disposed on the P substrate;
an oxide layer on the N band;
a first material having a positive Seebeck coefficient disposed in a first trench that extends through the oxide layer, through the N band and into the P substrate;
a second material having a negative Seebeck coefficient disposed in a second trench that extends through the oxide layer to the N band such that a bottom of the second trench is above and physically separated from a top surface of the P substrate, wherein portions of the oxide layer and the N band are positioned laterally between the first material in the first trench and the second material in the second trench;
a first contact on the first material and providing contact with a metal layer; and,
a second contact on the second material and providing contact with the metal layer.
2. The semiconductor structure of claim 1 , wherein the first material having the positive Seebeck coefficient is p+ polysilicon and the second material having the negative Seebeck coefficient is n+ polysilicon.
3. The semiconductor structure of claim 1 , further comprising oxide ring spacers in upper portions of the first trench and the second trench.
4. The semiconductor structure of claim 1 , wherein the metal layer is cooled when either the metal layer is biased to a power supply voltage and the P substrate is biased to ground or the metal layer is biased to ground and the P substrate is biased to a difference between ground and a portion of additional voltage bias.
5. The semiconductor structure of claim 1 , further comprising an inverter power rail in the metal layer and electrically connected to the first contact and the second contact, the inverter power rail comprising n+ Peltier contacts on a first side of a PFET and on a first side of an NFET and p+ Peltier contacts on a second side of the PFET and on a second side of the NFET.
6. The semiconductor structure of claim 5 , wherein, when the P substrate is biased at a voltage below ground and the N band is biased at a voltage above a power supply voltage:
a first current flow is from the first contact, into the first material, and to the P substrate;
a second current flow is from the N band, into the second material, and to the second contact;
the first material provides a first heat flow from the metal layer into the P substrate; and
the second material provides a second heat flow from the metal layer into the N band.
7. The semiconductor structure of claim 1 , wherein one of the metal layer and either the P substrate or the N band is configured to be biased with a power supply voltage and the other of the metal layer and either the P substrate or the N band is configured to be biased to ground.
8. A semiconductor structure comprising:
a P substrate;
an N band disposed on the P substrate;
an oxide layer on the N band;
a first material having a positive Seebeck coefficient disposed in a first trench that extends through the oxide layer to the N band;
a second material having a negative Seebeck coefficient disposed in a second trench that extends through the oxide layer to the N band;
a first contact on the first material and providing contact with a metal layer;
a second contact on the second material and providing contact with the metal layer; and,
an inverter power rail electrically connected to the first contact and the second contact.
9. The semiconductor structure of claim 8 , wherein the first material having the positive Seebeck coefficient is any of p+ polysilicon and tungsten and the second material having the negative Seebeck coefficient is n+ polysilicon.
10. The semiconductor structure of claim 8 , further comprising oxide ring spacers in upper portions of the first trench and the second trench.
11. The semiconductor structure of claim 8 , wherein, when a junction between the first material and the N band is forward biased, heat flows through the first material and the second material to the P substrate.
12. The semiconductor structure of claim 11 , wherein a junction between the N band and the P substrate is unbiased.
13. The semiconductor structure of claim 8 , the inverter power rail comprising n+ Peltier contacts on a first side of a PFET and on a first side of an NFET and p+ Peltier contacts on a second side of the PFET and on a second side of the NFET.
14. The semiconductor structure of claim 8 , further comprising a moat extending through the oxide layer, the N band and into the P substrate.
15. A semiconductor structure comprising:
a P substrate;
an N band disposed on the P substrate;
an oxide layer on the N band;
a first material having a positive Seebeck coefficient disposed in a first trench that extends through the oxide layer, through the N band and into the P substrate;
a second material having a negative Seebeck coefficient disposed in a second trench that extends through the oxide layer to the N band;
a first contact on the first material and providing contact with a metal layer;
a second contact on the second material and providing contact with the metal layer; and
oxide ring spacers in upper portions of the first trench and the second trench.
16. The semiconductor structure of claim 15 , wherein the first material having the positive Seebeck coefficient is p+ polysilicon and the second material having the negative Seebeck coefficient is n+ polysilicon.
17. The semiconductor structure of claim 15 , wherein the metal layer is cooled when either the metal layer is biased to a power supply voltage and the P substrate is biased to ground or the metal layer is biased to ground and the P substrate is biased to a difference between ground and a portion of additional voltage bias.
18. The semiconductor structure of claim 15 , further comprising an inverter power rail in the metal layer and electrically connected to the first contact and the second contact, the inverter power rail comprising n+ Peltier contacts on a first side of a PFET and on a first side of an NFET and p+ Peltier contacts on a second side of the PFET and on a second side of the NFET.
19. The semiconductor structure of claim 18 , wherein, when the P substrate is biased at a voltage below ground and the N band is biased at a voltage above a power supply voltage:
a first current flow is from the first contact, into the first material, and to the P substrate;
a second current flow is from the N band, into the second material, and to the second contact;
the first material provides a first heat flow from the metal layer into the P substrate; and
the second material provides a second heat flow from the metal layer into the N band.
20. The semiconductor structure of claim 15 , wherein one of the metal layer and either the P substrate or the N band is configured to be biased with a power supply voltage and the other of the metal layer and either the P substrate or the N band is configured to be biased to ground.