Resistive memory having confined filament formation
Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
1. A method of processing a resistive memory cell, comprising:
forming a stack having a silicon material and a first oxide material on the silicon material;
forming an opening in the stack;
forming a second oxide material in a portion of the opening in the stack adjacent the silicon material by oxidizing the silicon material adjacent the portion of the opening in the stack such that a portion of the silicon material is consumed; and
forming an ion source material in the opening in the stack directly contacting respective sidewalls of the first oxide material and the second oxide material.
2. The method of claim 1 , wherein the portion of the silicon material that is consumed comprises sides of the silicon material that define sidewalls of the opening in the stack.
3. The method of claim 1 , wherein the stack further includes a resistive memory material on which the silicon material is formed.
4. The method of claim 1 , wherein the second oxide material is formed in the opening in the stack such that the second oxide material does not completely fill the opening in the stack.
5. The method of claim 1 , wherein the ion source material is copper telluride.
6. The method of claim 1 , wherein the ion source material is silver sulfide.
7. The method of claim 1 , wherein the method includes forming the second oxide material in a lower portion of the opening in the stack adjacent the silicon material.
8. A method of processing a resistive memory cell, comprising:
forming a stack having an electrode, a silicon material on the electrode, and a first oxide material on the silicon material;
forming an opening in the stack;
forming a second oxide material in a portion of the opening in the stack adjacent the silicon material and on the electrode; and
forming a resistive memory material in the opening in the stack directly contacting respective sidewalls of the first oxide material and the second oxide material.
9. The method of claim 8 , wherein the method includes forming an ion source material in the opening in the stack adjacent, between, and on the resistive memory material.
10. The method of claim 8 , wherein the resistive memory material is formed in the opening in the stack such that the resistive memory material does not completely fill the opening in the stack.
11. The method of claim 8 , wherein the method includes forming the second oxide material in the opening in the stack by:
selectively forming a metal material in the opening in the stack adjacent the silicon material and on a portion of the electrode; and
oxidizing the metal material to form a metal oxide material in the opening in the stack adjacent the silicon material and on the electrode.
12. The method of claim 8 , wherein the method includes forming the second oxide material in the opening in the stack by oxidizing the silicon material adjacent the opening in the stack such that a portion of the silicon material is consumed and a silicon dioxide material is formed in the opening in the stack adjacent the silicon material and on the electrode.
13. The method of claim 8 , wherein the method includes forming the second oxide material in the opening in the stack such that the second oxide material does not form adjacent an upper sidewall of the first oxide material.
14. A resistive memory cell, comprising:
a vertical stack having:
an electrode;
a silicon material on and directly contacting the electrode;
a first oxide material on the silicon material;
a second oxide material formed on a sidewall of the silicon material; and
a resistive memory material directly contacting opposing sidewalls of the first oxide material and opposing sidewalls of the second oxide material in an area enclosed by the second oxide material.
15. The resistive memory cell of claim 14 , wherein the resistive memory material does not completely fill the area enclosed by the second oxide material.
16. The resistive memory cell of claim 14 , wherein the area enclosed by the second oxide material has a width of 5 to 15 nanometers.
17. The resistive memory cell of claim 14 , wherein the second oxide material is a metal oxide material.
18. The resistive memory cell of claim 14 , wherein the second oxide material is a silicon dioxide material.
19. The resistive memory cell of claim 14 , wherein the second oxide material is on and directly contacting the electrode.