IP Library Granted Patent US 10,551,428
Granted Patent B2
US 10,551,428 · App. 15/685,570 · Granted Feb 4, 2020

Systems and methods for storing frequency information for system calibration/trimming

Inventors: Ajay Kumar (Phoenix, AZ); Hyunsoo Yeom (Chandler, AZ)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
G01R31/2824G01R31/2837H03L1/00H03L1/021H03L1/026H03L7/02H03J2200/01H03J2200/10H03K2217/94031
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,551,428
App. No.
15/685,570
Granted
Feb 4, 2020
Kind
B2
Abstract

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

Claims (82)

1. An integrated circuit, comprising:

a frequency test circuit;

a device-under-test (DUT) having an input; and

a calculation engine circuit configured to:

compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency value stored in memory; and

based on the comparison, adjust a frequency of the DUT generating the DUT input;

wherein the frequency test circuit comprises a test resistor to which a test current can be applied and the calculation engine circuit is further configured to adjust frequency of the DUT based upon a predefined stress ratio stored in memory reflecting a status of the integrated circuit before and after packaging;

wherein to calculate said predefined stress ratio the calculation engine circuit is further configured to:

measure and store a first digital code for a desired frequency at a first temperature before packaging and a second digital code corresponding to a product of the test current and a resistance of the test resistor at the first temperature after packaging; and

obtain the predefined stress ratio by dividing the first digital code by the second digital code or vice versa.

2. The integrated circuit of claim 1 , wherein:

the frequency test circuit includes one or more switches and a capacitor; and

the frequency test circuit is configured to operate the one or more switches according to a an operating frequency of the DUT.

3. The integrated circuit of claim 1 , wherein:

the integrated circuit further includes an analog-to-digital converter (ADC);

the frequency test circuit includes one or more switches and a capacitor;

the frequency test circuit is configured to operate the one or more switches according to frequency of the DUT input;

the frequency test circuit is configured to output a voltage resulting from operation of the one or more switches according to frequency of the DUT input, the voltage output resulting from operation of the one or more switches to the ADC; and

the ADC is configured to output the measured frequency from a conversion of the voltage resulting from operation of the one or more switches.

4. The integrated circuit of claim 1 , wherein the calculation engine circuit is further configured to determine a temperature ratio by measuring and storing a first product of current and resistance values of said test resistor at the first temperature and a second product of current and resistor values of said test resistor at a second temperature different from the first temperature.

5. The integrated circuit of claim 1 , wherein the calculation engine circuit is further configured to adjust frequency of the DUT based upon a temperature ratio stored in memory reflecting a temperature performance curve.

6. The integrated circuit of claim 1 , further comprising:

a reference frequency input receiving the reference frequency value; and

a multiplexer configured to select between the DUT input and the reference frequency input to be applied to the frequency test circuit, wherein for determining the reference frequency value the integrated circuit controls the multiplexer to select the reference frequency input.

7. The integrated circuit of claim 6 ,

wherein when the reference frequency input is selected, the frequency test circuit is configured to store a resulting measurement to memory.

8. The integrated circuit of claim 1 , further comprising:

a reference frequency input receiving the reference frequency value; and

a multiplexer configured to select between the DUT input and the reference frequency input to be applied to the frequency test circuit;

wherein the frequency test circuit is configured to store a resulting reference frequency value to memory based upon a selection of the reference frequency input.

9. The integrated circuit of claim 1 , further comprising:

a reference frequency input receiving the reference frequency value; and

a multiplexer configured to select between the DUT input and the reference frequency input to be applied to the frequency test circuit;

wherein the frequency test circuit is configured to provide a resulting measurement of the DUT input to the calculation engine circuit based upon a selection of the DUT input.

10. A microcontroller, comprising:

a frequency test circuit comprising a test resistor to which a test current can be applied;

a device-under-test (DUT) having an input; and

a calculation engine circuit configured to:

compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency value stored in memory; and

based on the comparison, adjust frequency of the DUT generating the DUT input;

wherein the calculation engine circuit is further configured to adjust frequency of the DUT based upon a stress ratio stored in memory reflecting a status of the microcontroller before and after packaging;

wherein to calculate said stress ratio the calculation engine circuit is further configured to:

measure and store a first digital code for a desired frequency at a first temperature before packaging and a second digital code corresponding to a product of the test current and a resistance of the test resistor at the first temperature after packaging; and

obtain the stress ratio by dividing the first digital code by the second digital code or vice versa.

11. The microcontroller of claim 10 , wherein:

the frequency test circuit includes one or more switches and a capacitor; and

the frequency test circuit is configured to operate the one or more switches according to an operating frequency of the DUT.

12. The microcontroller of claim 10 , wherein:

the microcontroller further includes an analog-to-digital converter (ADC);

the frequency test circuit includes one or more switches and a capacitor;

the frequency test circuit is configured to operate the one or more switches according to frequency of the DUT input;

the frequency test circuit is configured to output a voltage resulting from operation of the one or more switches according to frequency of the DUT input, the voltage output resulting from operation of the one or more switches to the ADC; and

the ADC is configured to output the measured frequency from a conversion of the voltage resulting from operation of the one or more switches.

13. The microcontroller of claim 10 , wherein the calculation engine circuit is further configured to determine a temperature ratio by measuring and storing a first product of current and resistance values of said test resistor at the first temperature and a second product of current and resistor values of said test resistor at a second temperature different from the first temperature.

14. The microcontroller of claim 10 , wherein the calculation engine circuit is further configured to adjust frequency of the DUT based upon a temperature ratio stored in memory reflecting a temperature performance curve.

15. The microcontroller of claim 10 , further comprising:

a reference frequency input receiving the reference frequency value; and

a multiplexer configured to select between the DUT input and the reference frequency input to be applied to the frequency test circuit, wherein for determining the reference frequency value the microcontroller controls the multiplexer to select the reference frequency input.

16. The microcontroller of claim 15 ,

wherein when the reference frequency input is selected, the frequency test circuit is configured to store a resulting measurement to memory.

17. The microcontroller of claim 16 , further comprising:

wherein the resulting measurement corresponds to the reference frequency value and the frequency test circuit is configured to store the resulting measurement of the reference frequency value to memory based upon the selection of the reference frequency input.

18. The microcontroller of claim 10 , further comprising:

a reference frequency input receiving the reference frequency value; and

a multiplexer configured to select between the DUT input and the reference frequency input to be applied to the frequency test circuit;

wherein the frequency test circuit is configured to provide a resulting measurement of the DUT input to the calculation engine circuit based upon a selection of the DUT input.

19. A method, comprising:

selecting an input mode of an integrated circuit, the integrated circuit operable in the input mode to store reference frequencies and wherein the integrated circuit comprises a test resistor to which a test current can be applied;

applying a reference frequency to a frequency test circuit of the integrated circuit;

measuring a resulting frequency from the frequency test circuit; and

storing a first digital code representing the resulting frequency at a first temperature to memory of the integrated circuit before packaging;

adjusting frequency of an integrated oscillator based upon a predefined stress ratio stored in memory reflecting a status of the integrated circuit before and after packaging;

wherein the predefined stress ration is calculated by:

applying the test current to the test resistor;

measuring and storing a second digital code corresponding to a product of the test current and a resistance of the test resistor at the first temperature after packaging; and

obtaining the predefined stress ratio by dividing the first digital code by the second digital code or vice versa.

20. The method of claim 19 , further comprising:

determining a temperature ratio by measuring and storing a first product of current and resistor values of said test resistor at the first temperature and a second product of current and resistor values of said test resistor at a second temperature different from the first temperature.

21. The microcontroller according to claim 10 , wherein the DUT is an integrated oscillator.

22. The microcontroller according to claim 10 , wherein the calculation engine circuit comprises:

a first controllable switch coupled between a voltage reference and a first terminal of a capacitor whose second terminal is coupled with ground;

a second controllable switch coupled between the first terminal of the capacitor and an input of an analog-to-digital converter.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2017
From: KUMAR, AJAY; YEOM, HYUNSOO
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 043401/0247 →
Continuity (2)
Provisional Application 62379632 · Aug 25, 2016
Related Publication 20180059171A1 · Mar 1, 2018