IP Library Granted Patent US 10,325,661
Granted Patent B2
US 10,325,661 · App. 15/686,510 · Granted Jun 18, 2019

Methods of programming memory

Inventors: Yijie Zhao (Boise, ID); Akira Goda (Boise, ID)
Assignee: Micron Technology, Inc.
G11C16/12G11C16/0483G11C16/10G11C16/3427G11C16/3454
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Quick Facts
Patent No.
US 10,325,661
App. No.
15/686,510
Granted
Jun 18, 2019
Kind
B2
Abstract

Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

Claims (34)

1. A method of programming a memory, comprising:

applying a programming voltage on an access line selected for a programming operation of a single page of the memory;

applying a second voltage on an access line unselected for the programming operation;

increasing the programming voltage for a first plurality of steps of the programming operation; and

increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

2. The method of claim 1 , further comprising returning to increasing the second voltage during a second portion of the programming operation.

3. The method of claim 2 , wherein returning to increasing the second voltage comprises returning to increasing the second voltage for a third plurality of steps of the programming operation.

4. The method of claim 1 , wherein the particular point is determined by a number of programming cycles having been reached.

5. The method of claim 1 , wherein the particular point is determined by completion of programming for a certain programming level.

6. The method of claim 1 , wherein the particular point is determined by a shift in pattern of a plurality of bit lines coupled to memory cells of the access line selected for programming from a first pattern, where both bit lines adjacent to a bit line inhibited from programming are not being inhibited from programming, being dominant, to a second pattern, where both bit lines adjacent to a bit line inhibited from programming are being inhibited from programming, being dominant.

7. The method of claim 1 , wherein the particular point is determined by reaching a determined threshold voltage for memory cells of the selected access line being programmed.

8. The method of claim 1 , wherein the particular point is determined by reaching a particular number of steps of the first plurality of steps.

9. A method of programming a memory, comprising:

applying a programming voltage on an access line selected for a programming operation of a single page of the memory;

applying a second voltage on an access line unselected for the programming operation;

developing a boosted channel voltage while applying the programming voltage and applying the second voltage, wherein the programming voltage is expected to increase a threshold voltage of a memory cell of the selected access line having the boosted channel voltage, and wherein the second voltage is expected to inhibit an increase of a threshold voltage of a memory cell of the unselected access line having the boosted channel voltage;

increasing the programming voltage for a first plurality of steps of the programming operation; and

increasing the second voltage for a second plurality of steps during a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

10. The method of claim 9 , wherein developing the boosted channel voltage comprises developing the boosted channel voltage for the memory cell of the selected access line and for memory cells of a plurality of access lines unselected for the programming operation.

11. The method of claim 10 , wherein developing the boosted channel voltage for the memory cell of the selected access line and for the memory cells of the plurality of access lines unselected for the programming operation comprises developing the boosted channel voltage for each memory cell connected in series with the memory cell of the selected access line.

12. The method of claim 11 , wherein developing the boosted channel voltage for the memory cell of the selected access line and for the memory cells of the plurality of access lines unselected for the programming operation further comprises developing the boosted channel voltage for each memory cell connected in series with the memory cell of the selected access line prior to the particular point of the programming operation, and developing the boosted channel voltage for less than all memory cells connected in series with the memory cell of the selected access line after the particular point of the programming operation.

13. The method of claim 10 , wherein developing the boosted channel voltage for the memory cell of the selected access line and for the memory cells of the plurality of access lines unselected for the programming operation comprises developing the boosted channel voltage for less than all memory cells connected in series with the memory cell of the selected access line.

14. The method of claim 9 , further comprising returning to increasing the second voltage during a second portion of the programming operation.

15. The method of claim 14 , wherein returning to increasing the second voltage during the second portion of the programming operation comprises returning to increasing the second voltage during the second portion of the programming operation less than a remaining portion of the programming operation.

16. The method of claim 14 , wherein returning to increasing the second voltage comprises returning to increasing the second voltage for a third plurality of steps of the programming operation.

17. The method of claim 9 , wherein the particular point is determined by a criterion selected from a group consisting of a number of programming cycles having been reached, completion of programming for a particular programming level, a shift from a CS 2 pattern dominating to a CS 0 pattern dominating, reaching a determined threshold voltage for memory cells of the selected access line being programmed, and reaching a particular number of steps of the first plurality of steps.

18. A method of programming a memory, comprising:

applying a programming voltage on an access line selected for a programming operation of a single page of the memory, the selected access line having a memory cell selected for the programming operation;

applying a second voltage on an access line unselected for the programming operation, the unselected access line having a memory cell unselected for the programming operation, wherein the selected memory cell and the unselected memory cell are connected in series;

developing a boosted channel voltage of the selected memory cell and the unselected memory cell while applying the programming voltage and applying the second voltage, wherein the programming voltage is expected to increase a threshold voltage of the selected memory cell, and wherein the second voltage is expected to inhibit an increase of a threshold voltage of the unselected memory cell;

increasing the programming voltage for a first plurality of steps of the programming operation; and

increasing the second voltage for a second plurality of steps during a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

19. The method of claim 18 , wherein decreasing the second voltage at the particular point of the programming operation comprises decreasing the second voltage to an initial voltage level of the second voltage.

20. The method of claim 18 , further comprising returning to increasing the second voltage for a third plurality of steps during a second portion of the programming operation after decreasing the second voltage at the particular point of the programming operation, wherein a number of steps of the second plurality of steps plus a number of steps of the third plurality of steps is less than a number of steps of the first plurality of steps.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
Continuity (4)
Continuation 15248130 · Aug 26, 2016
Division 14633287 · Feb 27, 2015
Continuation 12702948 · Feb 9, 2010
Related Publication 20170358359A1 · Dec 14, 2017