Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same
The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.
1. A gate all-around integrated circuit structure comprising:
a first insulator region within a substrate;
a pair of remnant liner stubs disposed within the first insulator region, wherein each remnant liner stub extends from a top surface of the first insulator region at least partially into the first insulator region;
a second insulator region laterally adjacent to the first insulator region within the substrate, the second insulator region including a dielectric liner and a dielectric fill, the dielectric liner being interposed between the dielectric fill and the first insulator region;
a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and
a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions,
wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.
2. The gate all-around integrated circuit structure of claim 1 , wherein the dielectric liner of the second insulator region is substantially aligned with the outer sidewall of each fin in the pair of fins.
3. The gate all around integrated circuit structure of claim 1 , wherein the second insulator region is substantially coplanar with the first insulator region.
4. The gate all-around integrated circuit structure of claim 1 , further comprising:
source/drain epitaxial regions on opposing sides of the gate structure and laterally abutting each fin in the pair of fins.
5. The gate all-around integrated circuit structure of claim 4 , further comprising:
a gate spacer substantially surrounding the gate structure and interposed between the gate structure and the source/drain epitaxial regions.
6. The gate all-around integrated circuit structure of claim 1 , wherein each fin in the pair of fins includes a gate all-around segmented fin having a set of vertically spaced nano-ellipses, wherein an axial portion of each vertically spaced nano-ellipse is substantially surrounded by the gate structure.
7. The gate all-around integrated circuit structure of claim 1 , wherein the first insulator region extends laterally beneath each fin in the pair of fins.