Current sense amplifier architecture and level shifter
A high side current sensing amplifier architecture is simplified and improved over prior art current sensing amplifier circuits by using chopping only, without requiring auto-zeroing, and by using a simpler (and faster) switched capacitor filter instead of an auto-zeroing integrator filter. Also, VIP (positive DC sense node) is merged with the VDDHV (power supply) node, such that the integrated circuit package requires only a single node (package pin) to accommodate both the VIP and VDDHV connections for the current sensing amplifier circuit, resulting in being able to use a smaller integrated circuit package. A small resistor is coupled between VIP and VDDHV to reduce the offset considerably. A low latency time high voltage level shifter is provided which is essential for precise chopping operation.
1. A method for providing current measurement with a high side current sensing amplifier, said method comprising the steps of:
providing a current sensing resistor coupled between a power supply voltage and a load coupled to the power supply through the current sensing resistor;
providing a first high voltage amplifier;
coupling an operating voltage input of the first high voltage amplifier to the power supply voltage;
coupling a non-inverting input of the first high voltage amplifier to the power supply voltage;
coupling a low resistance value resistor between the operating voltage input and the non-inverting input of the first high voltage amplifier;
coupling an inverting input of the first high voltage amplifier to the load;
providing a first low voltage amplifier;
coupling a non-inverting input of the first low voltage amplifier to a reference voltage;
coupling an inverting input of the first low voltage amplifier to a feedback voltage;
coupling differential outputs of the first low voltage amplifier to differential outputs of the first high voltage amplifier;
coupling the differential outputs of the first high voltage and first low voltage amplifiers to differential outputs of a third low voltage amplifier;
coupling the differential outputs of the third low voltage amplifier to differential inputs of an operational amplifier output buffer;
providing a chopping circuit, wherein the chopping circuit comprises:
a first chopping switch coupled between the differential inputs of the first high voltage amplifier and differential inputs of a second high voltage amplifier;
a second chopping switch coupled between the differential inputs of the first low voltage amplifier and differential inputs of a second low voltage amplifier;
a third chopping switch coupled to differential outputs of the second high voltage amplifier and differential outputs of the second low voltage amplifier;
wherein the differential outputs of the second high voltage amplifier are coupled to the differential outputs of the second low voltage amplifier; and
a low pass filter coupled between outputs of the third chopping switch and the differential inputs of the third low voltage amplifier.
2. The method according to claim 1 , further comprising the steps of providing a high voltage level shifter circuit with a high voltage clock output, wherein the high voltage level shifter circuit comprises the steps of:
providing a low voltage oscillator circuit operating at N-times a chopping frequency, where N is equal to or greater than two (2); and
proving a high voltage divide-by-N circuit having an input coupled to the low voltage oscillator circuit and providing a high voltage clock output at the chopping frequency;
wherein one edge of the low voltage oscillator circuit is used to regenerate the high voltage clock output.
3. An amplifier architecture fabricated on an integrated circuit (IC) die, comprising:
a first IC die pad adapted for coupling to a power supply voltage and coupled to an operating voltage input (VDDHV) of an amplifier;
a second die pad adapted for coupling to the power supply voltage and coupled to a non-inverting input (VIP) of the amplifier;
a third die pad coupled to an inverting input (VIM) of the amplifier and adapted for coupling to a sense resistor coupled to a load, wherein the sense resistor is coupled between the power supply voltage and the load;
a resistor (Rs) is fabricated on the IC die and coupled between the first and second die pads, whereby induced voltage offset of the amplifier is reduced; and
a single electrostatic discharge (ESD) circuit coupled to the second die pad and providing ESD protection for both the operating voltage input and the non-inverting input of the amplifier.
4. The amplifier architecture according to claim 3 , is adapted for use in any self-correcting offset system, such as auto-zero and chopper stabilized circuits.
5. A current sensing amplifier, comprising:
a first high voltage amplifier fabricated on an integrated circuit (IC) die and having
an operating voltage input (VDDHV) adapted for coupling to a high voltage supply,
a first input (VIP) and a second input (VIM) adapted for coupling to a current sense resistor coupled between the high voltage supply and a load, wherein the first input (VIP) is coupled to the high voltage supply side of the current sense resistor and the second input (VIM) is coupled to the load side of the current sense resistor;
a resistor (Rs) fabricated on the IC die and coupled between the operating voltage input (VDDHV) and the first input (VIP) of the first high voltage amplifier;
a first low voltage amplifier having first and second inputs adapted for coupling to a reference voltage (VREF) and a feedback voltage (VFBK), respectively; and
first and second outputs of the first high voltage amplifier are coupled to first and second outputs, respectively, of the first low voltage amplifier; and
a third low voltage amplifier having first and second inputs coupled to first and second outputs of the first high voltage and first low voltage amplifiers, respectively; and
an operational amplifier output buffer having differential inputs coupled to the differential outputs of the first high and low voltage amplifiers.
6. The current sensing amplifier according to claim 5 , further comprising a chopping circuit coupled between the first and second inputs of the first high and low voltage amplifiers, and the differential inputs of the operational amplifier output buffer.
7. The current sensing amplifier according to claim 6 , wherein the chopping circuit comprises:
a first chopping switch coupled between the first and second inputs of the first high voltage amplifier and first and second inputs of a second high voltage amplifier;
a second chopping switch coupled between the first and second inputs of the first low voltage amplifier and first and second inputs of a second low voltage amplifier;
a third chopping switch coupled to first and second outputs of the second high voltage amplifier and first and second outputs of the second low voltage amplifier;
wherein the first and second outputs of the second high voltage amplifier are coupled to the first and second outputs of the second low voltage amplifier;
a low pass filter coupled to first and second outputs of the third chopping switch; and
a third low voltage amplifier having first and second inputs coupled to first and second outputs of the low pass filter, and first and second outputs coupled to the first and second outputs of the first high and low voltage amplifiers, respectively.
8. The current sensing amplifier according to claim 7 , wherein the high voltage amplifiers are transconductance amplifiers.
9. The current sensing amplifier according to claim 7 , wherein the low voltage amplifiers are transconductance amplifiers.
10. The current sensing amplifier according to claim 7 , wherein the low pass filter is a switched capacitor low pass filter.
11. The current sensing amplifier according to claim 7 , further comprising a high voltage level shifter circuit for providing a high voltage clock output.
12. The current sensing amplifier according to claim 11 , wherein the high voltage level shifter circuit comprises:
a low voltage oscillator circuit operating at N-times a chopping frequency, where N is equal to or greater than two (2); and
a high voltage divide-by-N circuit having an input coupled to the low voltage oscillator circuit and providing a high voltage clock output at the chopping frequency;
wherein one edge of the low voltage oscillator circuit is used to regenerate the high voltage clock output.
13. The current sensing amplifier according to claim 5 , further comprising an electrostatic discharge protection circuit coupled to the first input of the first high voltage amplifier.
14. The current sensing amplifier according to claim 5 , wherein the first amplifier input is a non-inverting input and the second amplifier input is an inverting input.