3D semiconductor device and structure
An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.
1. An Integrated Circuit device, the device comprising:
a base wafer comprising a single crystal layer, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors,
wherein said base wafer comprises a memory bit-cell array comprising said first transistors and control bit-lines and word-lines; and
a second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,
wherein said second layer comprises a connecting via to said bit-lines or said word-lines, said connecting via has a diameter of less than 200 nm, and
wherein said second layer comprises control circuits to control said memory bit-cell array, said control circuits comprise said second transistors.
2. The Integrated Circuit device according to claim 1 ,
wherein said second layer comprises an input-output (I/O) circuit to interface to external circuits, and
wherein said I/O circuit comprises said second transistors.
3. The Integrated Circuit device according to claim 1 , further comprising:
at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.
4. The Integrated Circuit device according to claim 1 ,
wherein said second layer thickness is less than 2 microns.
5. The Integrated Circuit device according to claim 1 ,
wherein said second layer comprises a single crystal layer.
6. The Integrated Circuit device according to claim 1 , further comprising:
a conductive layer disposed underneath said second layer,
wherein said conductive layer provides power to at least one of said second transistors.
7. The Integrated Circuit device according to claim 1 , and further comprising:
a third layer,
wherein said third layer comprises input-output circuits (“IOs”) designed to interface to external devices.
8. An Integrated Circuit device, the device comprising:
a base wafer comprising a single crystal layer, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors,
wherein said base wafer comprises a first memory bit-cell array comprising said first transistors and control first bit-lines and first word-lines; and
a second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,
wherein said second layer comprises a second memory bit-cell array comprising said second transistors and control second bit-lines and second word-lines,
wherein said second layer comprises a connecting via from at least one of said second bit-lines or said second word-lines to at least one of said first bit-lines or said first word-lines, and
wherein said connecting via has a diameter of less than 200 nm.
9. The Integrated Circuit device according to claim 8 ,
wherein said second layer comprises an I/O circuit to interface to external circuits, and
wherein said I/O circuit comprises said second transistors.
10. The Integrated Circuit device according to claim 8 , further comprising:
at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.
11. The Integrated Circuit device according to claim 8 ,
wherein said second layer thickness is less than 2 microns.
12. The Integrated Circuit device according to claim 8 , further comprising:
a third layer,
wherein said third layer comprises control circuits to control said second memory bit-cell array.
13. An Integrated Circuit device according to claim 8 , further comprising:
a third layer,
wherein said third layer comprises control circuits to control said second memory bit-cell array; and
a connecting via,
wherein said connecting via is connecting said control circuits to at least one of said second bit-lines or said second word-lines, and
wherein said connecting via has a diameter of less than 200 nm.
14. The Integrated Circuit device according to claim 8 , further comprising:
a third layer overlying said second layer,
wherein said third layer comprises an I/O circuit, said I/O circuit is adapted to interface with an external circuit.
15. An Integrated Circuit device, the device comprising:
a base wafer comprising a single crystal layer, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors,
wherein said base wafer comprises a memory bit-cell array comprising said first transistors and control bit-lines and word-lines; and
a second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,
wherein said second layer comprises a connecting via to said bit-lines or word-lines, said connecting via has a diameter of less than 200 nm,
wherein said second layer comprises an input-output (I/O) circuit to interface to external circuits, and
wherein said I/O circuit comprises said second transistors.
16. The Integrated Circuit device according to claim 15 ,
wherein said second layer thickness is less than 2 microns.
17. The Integrated Circuit device according to claim 15 , further comprising:
at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.
18. The Integrated Circuit device according to claim 15 , further comprising:
a third layer, said third layer disposed between said second layer and said single crystal layer,
wherein said third layer comprises control circuits to control said memory bit-cell array.
19. The Integrated Circuit device according to claim 15 ,
wherein said second layer further comprises control circuits to control said memory bit-cell array.
20. The Integrated Circuit device according to claim 19 , further comprising:
a third layer, said third layer disposed between said second layer and said single crystal layer,
wherein said third layer thickness is less than 2 microns.