Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof
View Patent ↗Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.
1. A method of manufacturing a semiconductor device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a plurality of memory openings through the stack;
forming memory stack structures in the plurality of memory openings, each of the memory stack structures comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a semiconductor channel;
forming a backside via trench through the alternating stack;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers employing an etchant introduced through the backside via trench;
depositing a silicon-containing layer in the backside recesses; and
forming a metal silicide layer and a metal portion in the backside recesses after depositing the silicon-containing layer,
wherein the metal silicide layer and the metal portion are formed in the backside recesses by:
depositing a metal element in remaining volumes of the backside recesses;
inducing silicidation of a portion of the deposited metal element,
wherein the silicon-containing layer is at least partially consumed during silicidation of the portion of the deposited metal element, and an unreacted portion of the deposited metal element constitutes the metal portion; and
wherein the silicon-containing layer is only partially consumed during the silicidation of the portion of the deposited metal element.
2. A method of manufacturing a semiconductor device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a plurality of memory openings through the stack;
forming memory stack structures in the plurality of memory openings, each of the memory stack structures comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a semiconductor channel;
forming a backside via trench through the alternating stack;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers employing an etchant introduced through the backside via trench;
depositing a silicon-containing layer in the backside recesses;
forming a metal silicide layer and a metal portion in the backside recesses after depositing the silicon-containing layer; and
removing the silicon-containing layer from the periphery of the backside via trench while a remaining portion of the silicon-containing layer is present in each of the backside recesses, wherein the metal element is deposited directly on a surface of the remaining portion of the silicon-containing layer.
3. The method of claim 2 , wherein:
the metal element comprises cobalt; and
the metal element is deposited by a selective chemical vapor deposition process or a selective atomic layer deposition process that deposits the metal element on the surface of the remaining portion of the silicon-containing layer at a greater deposition rate than on physically exposed surfaces in the backside via trench.
4. The method of claim 3 , further comprising:
depositing a metal nitride layer in the backside recesses prior to depositing the silicon-containing layer, wherein the silicon-containing layer is deposited directly on the metal nitride layer and the physically exposed surfaces in the backside via trench comprise a surface of a metal nitride layer; and
removing portions of the metal nitride layer from the periphery of the backside via trench after formation of the metal portion in the backside recesses.
5. A method of manufacturing a semiconductor device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a plurality of memory openings through the stack;
forming memory stack structures in the plurality of memory openings, each of the memory stack structures comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a semiconductor channel;
forming a backside via trench through the alternating stack;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers employing an etchant introduced through the backside via trench;
depositing a silicon-containing layer in the backside recesses; and
forming a metal silicide layer and a metal portion in the backside recesses after depositing the silicon-containing layer,
wherein:
the metal silicide layer is an amorphous or microcrystalline metal silicide layer, and the metal portion comprises a tungsten layer having an average grain size greater than 40 nm and a resistivity of less than 20 Ohm-cm;
the silicon-containing layer includes silicon at an atomic concentration of at least 60%;
the tungsten layer have an average grain size of 60 to 90 nm and a resistivity of 15 to 18 Ohm-cm;
the metal silicide layer comprises amorphous tungsten silicide or microcrystalline tungsten silicide having an average grain size of less than 3 nm;
depositing the silicon-containing layer comprises depositing an in-situ boron-doped silicon layer using diborane as a dopant in a first chamber; and
forming the metal silicide layer comprises depositing a tungsten layer on the boron-doped silicon layer in the first chamber without a vacuum break, followed by reacting the tungsten layer with the boron-doped silicon layer to form the amorphous or microcrystalline tungsten silicide layer.
6. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
a memory stack structure extending through the alternating stack and comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a vertical semiconductor channel;
wherein each of the electrically conductive layers comprises:
a metal silicide layer;
a metal portion contacting horizontal surfaces and an outer sidewall of the metal silicide layer; and
a silicon-containing layer that includes silicon at an atomic concentration of at least 60%, is essentially free of the metal element, and located between the memory stack structures and the metal silicide layer.
7. The three-dimensional memory device of claim 6 , further comprising:
a backside via trench vertically extending through each layer within the alternating stack; and
a dielectric material portion located in the backside via trench and extending through each layer within the alternating stack,
wherein each silicon-containing layer and each metal portion of the electrically conductive layers directly contact a sidewall of the dielectric material portion.
8. The three-dimensional memory device of claim 6 , further comprising:
a backside via trench vertically extending through each layer within the alternating stack; and
a dielectric material portion located in the backside via trench and extending through each layer within the alternating stack, wherein:
each metal portion of the electrically conductive layers directly contacts a sidewall of the dielectric material portion; and
each silicon-containing layer of the electrically conductive layers does not directly contact, and is laterally spaced by a respective metal portion from, the dielectric material portion.
9. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
a memory stack structure extending through the alternating stack and comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a vertical semiconductor channel;
wherein each of the electrically conductive layers comprises:
a metal silicide layer;
a metal portion contacting horizontal surfaces and an outer sidewall of the metal silicide layer; and
a metal nitride layer located between the memory stack structures and the metal silicide layer.
10. The three-dimensional memory device of claim 9 , further comprising:
a backside via trench vertically extending through each layer within the alternating stack; and
a dielectric material portion located in the backside via trench and extending through each layer within the alternating stack,
wherein each metal nitride layer and each metal portion of the electrically conductive layers directly contact a sidewall of the dielectric material portion.
11. The three-dimensional memory device of claim 9 , further comprising:
a backside via trench vertically extending through each layer within the alternating stack; and
a dielectric material portion located in the backside via trench and extending through each layer within the alternating stack,
wherein:
each metal portion of the electrically conductive layers directly contacts a sidewall of the dielectric material portion; and
each metal nitride layer of the electrically conductive layers does not directly contact, and is laterally spaced by a respective metal portion from, the dielectric material portion.
12. The three-dimensional memory device of claim 9 , wherein the metal silicide layer directly contacts horizontal surfaces of a respective one of the metal nitride layers of the electrically conductive layers.
13. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
a memory stack structure extending through the alternating stack and comprising, from outside to inside, a memory material layer, a tunneling dielectric layer, and a vertical semiconductor channel;
wherein each of the electrically conductive layers comprises:
a metal silicide layer; and
a metal portion contacting horizontal surfaces and an outer sidewall of the metal silicide layer; and
wherein the metal silicide layer has a gradient in atomic concentration of silicon such that the atomic concentration of silicon increases with distance from an interface between the metal silicide layer and the metal portion.