Memory device having programmable impedance elements with a common conductor formed below bit lines

1. An integrated circuit (IC) device, comprising:

a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction;

a plurality of two-terminal programmable impedance elements formed over the substrate, each programmable impedance element programmable between at least two different impedance values;

at least one conductive plate structure formed on and having a common conductive connection to, multiple rows and columns of the programmable impedance elements, the at least one conductive plate structure extending in at least the first direction;

a plurality of storage contacts, each storage contact extending from a first current terminal of each access transistor to one of the programmable impedance elements;

a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and

a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one conductive plate structure to one of the bit lines; wherein

the access transistors and programmable impedance elements form memory cells that each include no more than one programmable impedance element.

2. The IC device of claim 1 , wherein:

the at least one conductive plate structure includes an opening corresponding to each bit line contact through which each bit line contact extends.

3. The IC device of claim 1 , wherein:

the at least one conductive plate structure includes openings through which multiple bit line contacts extend.

4. The IC device of claim 1 , wherein:

the at least one conductive plate structure includes a plurality of elongated plate members that extend in the first direction, the bit line contacts extending between the elongated plate members to the bit lines.

5. The IC device of claim 1 , further including:

a plate tap structure having a conductive connection to the at least one conductive plate structure, and configured to apply a variable plate voltage to the at least one conductive plate structure.

6. The IC device of claim 1 , wherein:

the plate tap structure includes

a plate voltage conductor formed over the at least one conductive plate structure, and

a plate tap via that extends from the at least one conductive plate structure to the plate voltage conductor.

7. The IC device of claim 1 , wherein:

the programmable impedance elements include at least one memory layer that is programmable between at least two different impedance states in response to electric fields that induce an oxidation-reduction reaction in the memory layer.

8. An integrated circuit (IC) device, comprising:

a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction;

a plurality of two-terminal programmable impedance elements formed over the substrate arranged into groups, each programmable impedance element programmable between at least two different impedance values;

a plurality of conductive plate structures, each formed on and having a common conductive connection to a different group of the programmable impedance elements, each group comprising multiple rows and columns of programmable impedance elements, each conductive plate structure extending in at least the first direction;

a plurality of storage contacts, each storage contact extending from a first current terminal of each access transistor to one of the programmable impedance elements;

a plurality of bit lines formed over the conductive plate structures, the bit lines extending in a second direction different from the first direction; and

a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the conductive plate structures to one of the bit lines; wherein

the access transistors and programmable impedance elements form memory cells that each include no more than one impedance element.

9. The IC device of claim 8 , wherein:

each storage contact includes at least a first type contact structure extending vertically from the substrate; and

each bit line contact includes at least a second type contact structure terminating at a greater vertical distance from the substrate than the first type contact structures.

10. The IC device of claim 9 , further including:

a plate tap structure having a conductive connection to at least one of the conductive plate structures that includes

a plate voltage conductor formed over the at least one conductive plate structure, and

a plate tap via that extends from the at least one conductive plate structure to the plate voltage conductor, the plate tap via terminating above the substrate at a same distance as the second type contact structures.

11. The IC device of claim 8 , wherein:

each storage contact includes at least a first type contact structure extending vertically from the substrate; and

each bit line contact includes at least the first type contact structure.

12. The IC device of claim 11 , wherein:

each bit line contact further includes at least a second type contact structure extending vertically from the corresponding first type contact structure.

13. The IC device of claim 1 , further including:

a plate tap structure patterned from a metallization layer formed above the conductive plate structures and having a conductive connection to at least one of the conductive plate structures.

14. The IC device of claim 8 , wherein:

the programmable impedance elements include at least one memory layer that is programmable between at least two different impedance states in response to electric fields including by an oxidation-reduction reaction in the memory layer.

15. An integrated circuit (IC) device, comprising:

a plurality of bit lines extending in a first direction;

at least one conductive plate structure formed between the bit lines and a substrate and extending in a second direction different from the first direction;

a plurality of two-terminal programmable impedance elements arranged into rows and columns and having a common conductive connection to the at least one conductive plate structure, each programmable impedance element programmable between at least two different impedance values;

a plurality of access transistors formed in the substrate having control terminals connected to word lines that extend in the second direction;

a plurality of bit line contacts that each extend from one of the bit lines through an opening in the at least one conductive plate structure to a first current terminal of one of the access transistors; and

a plurality of storage contacts that each extend from one programmable impedance element to a second current terminal of one of the corresponding access transistors; and

each access transistor and its one corresponding programmable impedance element form one memory cell.

16. The IC device of claim 15 , wherein:

the at least one conductive plate structure includes a plurality of plate members that extend in the second direction.

17. The IC device of claim 15 , wherein:

the programmable impedance elements include at least one memory layer that is programmable between at least two different impedance states in response to electric fields including by an oxidation-reduction reaction in the memory layer.