Chip package having die structures of different heights
Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.
1. A package comprising:
a substrate;
a first chip stack bonded to the substrate, the first chip stack having a first height;
a second chip stack bonded to the substrate adjacent the first chip stack, the second chip stack having the first height;
a semiconductor chip bonded to the substrate between the first chip stack and the second chip stack, the semiconductor chip having a second height greater than the first height; and
a molding compound layer extending along a first side of the first chip stack, the first side of the first chip stack being a farthest side of the first chip stack from the substrate, a topmost surface of the molding compound layer being substantially level with a topmost surface of the semiconductor chip.
2. The package of claim 1 , further comprising an underfill layer interposed between the substrate and the molding compound layer.
3. The package of claim 2 , wherein a topmost surface of the underfill layer is above a bottommost surface of the first chip stack and a bottommost surface of the second chip stack.
4. The package of claim 1 , further comprising first connectors between the first chip stack and the substrate, the first connectors electrically and mechanically coupling the first chip stack to the substrate.
5. The package of claim 4 , further comprising second connectors between the second chip stack and the substrate, the second connectors electrically and mechanically coupling the second chip stack to the substrate.
6. A package comprising:
a substrate;
a first semiconductor chip attached to the substrate;
a second semiconductor chip attached to the substrate laterally adjacent the first semiconductor chip, a sidewall of the first semiconductor chip facing a sidewall of the second semiconductor chip, a top surface of the second semiconductor chip being above a top surface of the first semiconductor chip, the first semiconductor chip and the second semiconductor chip being attached to a same side of the substrate; and
a molding compound layer surrounding the first semiconductor chip and the second semiconductor chip, the molding compound layer overfilling a gap between the first semiconductor chip and the second semiconductor chip, a top surface of the molding compound layer being level with the top surface of the second semiconductor chip, the molding compound layer covering the top surface of the first semiconductor chip.
7. The package of claim 6 , wherein the second semiconductor chip is exposed through the molding compound layer.
8. The package of claim 6 , wherein the second semiconductor chip has a greater height than the first semiconductor chip.
9. The package of claim 6 , further comprising an underfill layer surrounding the first semiconductor chip and the second semiconductor chip, an interface between the underfill layer and the molding compound layer being above a bottommost surface of the first semiconductor chip and a bottommost surface of the second semiconductor chip.
10. The package of claim 9 , wherein a first size of first fillers dispersed in the molding compound layer is less than a second size of second fillers dispersed in the underfill layer.
11. The package of claim 9 , wherein a first density of first fillers dispersed in the molding compound layer is less than a second density of second fillers dispersed in the underfill layer.
12. The package of claim 9 , further comprising connectors between the first semiconductor chip and the substrate, the connectors being surrounded by the underfill layer.
13. A package comprising:
a substrate;
a semiconductor chip bonded to the substrate, the semiconductor chip having a topmost surface facing away from the substrate, the topmost surface of the semiconductor chip being spaced apart from the substrate by a first distance;
a first chip stack bonded to the substrate, the first chip stack having a topmost surface facing away from the substrate, the topmost surface of the first chip stack being spaced apart from the substrate by a second distance, the second distance being less than the first distance;
an underfill layer extending between the semiconductor chip and the substrate and between the first chip stack and the substrate, at least a portion of the underfill layer extending along sidewalls of the semiconductor chip and along sidewalls of the first chip stack; and
a package layer over the underfill layer, the package layer completely filling a gap between the semiconductor chip and the first chip stack, the package layer extending along the topmost surface of the first chip stack, a topmost surface of the package layer being substantially level with the topmost surface of the semiconductor chip, an interface between the underfill layer and the package layer being above a bottommost surface of the first chip stack and below the topmost surface of the first chip stack.
14. The package of claim 13 , wherein the first chip stack comprises:
a plurality of dies; and
an encapsulant extending along sidewalls of the plurality of dies and across the interface between the underfill layer and package layer.
15. The package of claim 14 , wherein the encapsulant extends along and physically contacts a topmost surface of at least one die of the plurality of dies.
16. The package of claim 13 , wherein a first size of first fillers dispersed in the underfill layer is less than a second size of second fillers dispersed in the package layer.
17. The package of claim 13 , wherein a first density of first fillers dispersed in the underfill layer is less than a second density of second fillers dispersed in the package layer.
18. The package of claim 6 , further comprising a third semiconductor chip attached to the substrate, the top surface of the second semiconductor chip being above a top surface of the third semiconductor chip, the molding compound layer covering the top surface of the third semiconductor chip.
19. The package of claim 13 , further comprising a second chip stack bonded to the substrate, the semiconductor chip being interposed between the first chip stack and the second chip stack, the second chip stack having a topmost surface facing away from the substrate, the topmost surface of the second chip stack being spaced apart from the substrate by a third distance, the third distance being less than the first distance.
20. The package of claim 19 , wherein the package layer extends along the topmost surface of the second chip stack, and wherein the interface between the underfill layer and the package layer is above a bottommost surface of the second chip stack and below the topmost surface of the second chip stack.