Semiconductor device assemblies and associated methods
A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.
1. A semiconductor device assembly, comprising:
an assembly substrate including a top surface;
a top semiconductor device including a bottom surface; and
a plurality of intermediary semiconductor devices, each bonded to both the assembly substrate top surface and to the top semiconductor device bottom surface, wherein each intermediary semiconductor device includes:
a memory array,
a first bond pad electrically coupling the intermediary semiconductor device to the assembly substrate,
a second bond pad electrically coupling the intermediary semiconductor device to the top semiconductor device, and
a passthrough conductive column extending through a semiconductor substrate of the intermediary semiconductor device from the first bond pad to the second bond pad, and exclusive of any electrical connection to the memory array.
2. The semiconductor device assembly of claim 1 , wherein the top semiconductor device further includes a bypass bond pad at the bottom surface electrically coupled to the assembly substrate via the second bond pad, the passthrough conductive column, and the first bond pad of one of the plurality of intermediary semiconductor devices.
3. The semiconductor device assembly of claim 1 , wherein the top semiconductor device further includes an intermediary bond pad at the bottom surface, wherein one of the plurality of intermediary semiconductor devices further includes a third bond pad electrically coupled to the intermediary bond pad, and wherein the top semiconductor device is electrically coupled to the memory array of the one of the plurality of intermediary semiconductor devices via the intermediary bond pad and the third bond pad.
4. The semiconductor device assembly of claim 1 , wherein the plurality of intermediary semiconductor devices are hybrid-bonded to the top semiconductor device.
5. The semiconductor device assembly of claim 1 , wherein the plurality of intermediary semiconductor devices are solder-bonded to the assembly substrate.
6. The semiconductor device assembly of claim 1 further comprising a mold material over the top surface of the assembly substrate and encasing the top semiconductor device and the plurality of intermediary semiconductor devices.
7. The semiconductor device assembly of claim 1 further comprising a mold material between the plurality of intermediary semiconductor devices.
8. The semiconductor device assembly of claim 1 further comprising an underfill material between the plurality of intermediary semiconductor devices and the assembly substrate.
9. A semiconductor device assembly, comprising:
a top semiconductor device including a bottom surface; and
a plurality of intermediary semiconductor devices, each bonded to the bottom surface, wherein each intermediary semiconductor device includes:
a memory array,
a first bond pad electrically coupled to the top semiconductor device,
a second bond pad opposite the first bond pad, and
a passthrough conductive column extending through a semiconductor substrate of the intermediary semiconductor device from the first bond pad to the second bond pad, and exclusive of any electrical connection to the memory array.
10. The semiconductor device assembly of claim 9 further comprising:
a plurality of second intermediary semiconductor devices, wherein each second intermediary semiconductor device is bonded to one of the plurality of intermediary semiconductor devices, and wherein each second intermediary semiconductor device includes:
a memory array,
a third bond pad electrically coupled to the top semiconductor device via the first bond pad, the second bond pad, and the passthrough conductive column,
a fourth bond pad opposite the third bond pad, and
a second passthrough conductive column extending through a semiconductor substrate of the second intermediary semiconductor device from the third bond pad to the fourth bond pad, and exclusive of any electrical connection to the memory array of the second intermediary semiconductor device.
11. The semiconductor device assembly of claim 10 further comprising an assembly substrate bonded to the plurality of second intermediary semiconductor devices opposite the bonds between the plurality of intermediary semiconductor devices and the plurality of second intermediary semiconductor devices.
12. The semiconductor device assembly of claim 10 , wherein one of the plurality of intermediary semiconductor devices and the second intermediary semiconductor device bonded thereto each further include an inter-device bond pad electrically coupling the memory array of the one of the plurality of intermediary semiconductor devices to the memory array of the second intermediary semiconductor device bonded thereto.
13. The semiconductor device assembly of claim 12 , wherein the top semiconductor device further includes an intermediary bond pad at the bottom surface, wherein the one of the plurality of intermediary semiconductor devices further includes a top bond pad, and wherein the intermediary bond pad and the top bond pad electrically couple the top semiconductor device to the memory array of the second intermediary semiconductor device bonded to the one of the plurality of intermediary semiconductor devices via the memory array of the one of the plurality of intermediary semiconductor device and the inter-device bond pads.
14. The semiconductor device assembly of claim 9 , wherein the plurality of intermediary semiconductor devices are hybrid-bonded to the top semiconductor device.
15. The semiconductor device assembly of claim 10 , wherein each of the plurality of second intermediary semiconductor devices is hybrid-bonded to the one of the plurality of intermediary semiconductor devices.
16. The semiconductor device assembly of claim 11 , wherein the assembly substrate is solder-bonded to the plurality of second intermediary semiconductor devices.
17. The semiconductor device assembly of claims 11 further comprising a mold material over a top surface of the assembly substrate and encasing the top semiconductor device, the plurality of intermediary semiconductor devices, and the plurality of second intermediary semiconductor devices.
18. A method of manufacturing a semiconductor device assembly, comprising:
forming a plurality of intermediary semiconductor devices, wherein each intermediary semiconductor device includes:
a memory array,
a first bond pad at a first surface of the intermediary semiconductor device,
a second bond pad at a second surface of the intermediary semiconductor device opposite the first surface, and
a passthrough conductive column extending through a semiconductor substrate of the intermediary semiconductor device from the first bond pad to the second bond pad, and exclusive of any electrical connection to the memory array;
bonding each of the plurality of the intermediary semiconductor devices directly to a top semiconductor device; and
bonding an assembly substrate directly to each of the plurality of intermediary semiconductor devices, electrically coupling the top semiconductor device to the assembly substrate via the first bond pads, the second bond pads, and the passthrough conductive columns.
19. The method of claim 18 further comprising:
providing mold material between the intermediary semiconductor devices after bonding each of the intermediary semiconductor devices directly to the top semiconductor device and before bonding the assembly substrate directly to each of the intermediary semiconductor devices;
providing an underfill material between the intermediary semiconductor devices and the assembly substrate after bonding the assembly substrate to each of the intermediary semiconductor devices; and
providing a mold material over the intermediary semiconductor devices and the top semiconductor device.
20. The method of claim 18 further comprising forming solder balls on the assembly substrate.